[llvm] 3b589fe - [tests] Add coverage for demanded bits of zext nneg

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-11-02T11:08:08-07:00
New Revision: 3b589fe6e68ce0b17515e4a88b5188abb8d6216d

URL: https://github.com/llvm/llvm-project/commit/3b589fe6e68ce0b17515e4a88b5188abb8d6216d
DIFF: https://github.com/llvm/llvm-project/commit/3b589fe6e68ce0b17515e4a88b5188abb8d6216d.diff

LOG: [tests] Add coverage for demanded bits of zext nneg

Precommit of tests from 70858, requested in review.

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/zext.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/zext.ll b/llvm/test/Transforms/InstCombine/zext.ll
index 255d9764410cd1e..9dd0d929530b333 100644
--- a/llvm/test/Transforms/InstCombine/zext.ll
+++ b/llvm/test/Transforms/InstCombine/zext.ll
@@ -5,6 +5,7 @@ target datalayout = "n64"
 
 declare void @use1(i1)
 declare void @use32(i32)
+declare void @use64(i64)
 declare void @use_vec(<2 x i9>)
 
 define i64 @test_sext_zext(i16 %A) {
@@ -777,3 +778,66 @@ define i64 @evaluate_zexted_const_expr(i1 %c) {
   %ext = zext i7 %and to i64
   ret i64 %ext
 }
+
+; FIXME: This is currently miscompiling as the and gets dropped,
+; but the flag on the zext doesn't.
+define i16 @zext_nneg_flag_drop(i8 %x, i16 %y) {
+; CHECK-LABEL: @zext_nneg_flag_drop(
+; CHECK-NEXT:    [[EXT:%.*]] = zext nneg i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[OR1:%.*]] = or i16 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i16 [[OR1]], 128
+; CHECK-NEXT:    ret i16 [[OR2]]
+;
+  %and = and i8 %x, 127
+  %ext = zext nneg i8 %and to i16
+  %or1 = or i16 %ext, %y
+  %or2 = or i16 %or1, 128
+  ret i16 %or2
+}
+
+define i32 @zext_nneg_redundant_and(i8 %a) {
+; CHECK-LABEL: @zext_nneg_redundant_and(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[A:%.*]], 127
+; CHECK-NEXT:    [[RES:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[RES]]
+;
+  %a.i32 = zext nneg i8 %a to i32
+  %res = and i32 %a.i32, 127
+  ret i32 %res
+}
+
+; Negative test, the and can't be removed
+define i32 @zext_nneg_redundant_and_neg(i8 %a) {
+; CHECK-LABEL: @zext_nneg_redundant_and_neg(
+; CHECK-NEXT:    [[B:%.*]] = and i8 [[A:%.*]], 127
+; CHECK-NEXT:    [[B_I32:%.*]] = zext nneg i8 [[B]] to i32
+; CHECK-NEXT:    ret i32 [[B_I32]]
+;
+  %b = and i8 %a, 127
+  %b.i32 = zext nneg i8 %b to i32
+  ret i32 %b.i32
+}
+
+define i64 @zext_nneg_signbit_extract(i32 %a) nounwind {
+; CHECK-LABEL: @zext_nneg_signbit_extract(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[A:%.*]], 31
+; CHECK-NEXT:    [[C:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    ret i64 [[C]]
+;
+  %b = zext nneg i32 %a to i64
+  %c = lshr i64 %b, 31
+  ret i64 %c
+}
+
+define i64 @zext_nneg_demanded_constant(i8 %a) nounwind {
+; CHECK-LABEL: @zext_nneg_demanded_constant(
+; CHECK-NEXT:    [[B:%.*]] = zext nneg i8 [[A:%.*]] to i64
+; CHECK-NEXT:    call void @use64(i64 [[B]]) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT:    [[C:%.*]] = and i64 [[B]], 254
+; CHECK-NEXT:    ret i64 [[C]]
+;
+  %b = zext nneg i8 %a to i64
+  call void @use64(i64 %b)
+  %c = and i64 %b, 254
+  ret i64 %c
+}