[llvm] AMDGPU: Support llvm.exp10 (PR #65860)

via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 2 06:36:42 PDT 2023


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff 7fa41d8a8f897219a6b22ab7a288f445e9d6119b 42206193b19c5b1555151d70e0143153fc3e50dc -- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
``````````

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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 4a2b8602b9a3..98127da4cfcb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -336,9 +336,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::FLOG2, MVT::f32, Custom);
   setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
 
-  setOperationAction({ISD::FLOG, ISD::FLOG10,
-                      ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32,
-                     Custom);
+  setOperationAction(
+      {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32,
+      Custom);
 
   setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom);
 
@@ -353,7 +353,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
     setOperationAction({ISD::FLOG2, ISD::FEXP2, ISD::FEXP10}, MVT::f16, Custom);
   }
 
-  setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, Custom);
+  setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16,
+                     Custom);
 
   // FIXME: These IS_FPCLASS vector fp types are marked custom so it reaches
   // scalarization code. Can be removed when IS_FPCLASS expand isn't called by
@@ -458,13 +459,13 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
 
   for (MVT VT : FloatVectorTypes) {
     setOperationAction(
-        {ISD::FABS,    ISD::FMINNUM,      ISD::FMAXNUM,   ISD::FADD,
-         ISD::FCEIL,   ISD::FCOS,         ISD::FDIV,      ISD::FREM,
-         ISD::FEXP2,   ISD::FEXP,         ISD::FEXP10,    ISD::FLOG2,
-         ISD::FLOG,    ISD::FLOG10,       ISD::FPOW,      ISD::FFLOOR,
-         ISD::FTRUNC,  ISD::FMUL,         ISD::FMA,       ISD::FRINT,
-         ISD::FNEARBYINT, ISD::FSQRT,     ISD::FSIN,      ISD::FSUB,
-         ISD::FNEG,    ISD::VSELECT,      ISD::SELECT_CC, ISD::FCOPYSIGN,
+        {ISD::FABS,           ISD::FMINNUM, ISD::FMAXNUM,      ISD::FADD,
+         ISD::FCEIL,          ISD::FCOS,    ISD::FDIV,         ISD::FREM,
+         ISD::FEXP2,          ISD::FEXP,    ISD::FEXP10,       ISD::FLOG2,
+         ISD::FLOG,           ISD::FLOG10,  ISD::FPOW,         ISD::FFLOOR,
+         ISD::FTRUNC,         ISD::FMUL,    ISD::FMA,          ISD::FRINT,
+         ISD::FNEARBYINT,     ISD::FSQRT,   ISD::FSIN,         ISD::FSUB,
+         ISD::FNEG,           ISD::VSELECT, ISD::SELECT_CC,    ISD::FCOPYSIGN,
          ISD::VECTOR_SHUFFLE, ISD::SETCC,   ISD::FCANONICALIZE},
         VT, Expand);
   }
@@ -2925,9 +2926,8 @@ SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
   // TODO: Interpret allowApproxFunc as ignoring DAZ. This is currently copying
   // library behavior. Also, is known-not-daz source sufficient?
   if (allowApproxFunc(DAG, Flags)) {
-    return IsExp10 ?
-      lowerFEXP10Unsafe(X, SL, DAG, Flags) :
-      lowerFEXPUnsafe(X, SL, DAG, Flags);
+    return IsExp10 ? lowerFEXP10Unsafe(X, SL, DAG, Flags)
+                   : lowerFEXPUnsafe(X, SL, DAG, Flags);
   }
 
   //    Algorithm:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 566b81256300..284241f51e9a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1170,8 +1170,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   Log2Ops.scalarize(0)
     .lower();
 
-  auto &LogOps = getActionDefinitionsBuilder({G_FLOG, G_FLOG10,
-                                              G_FEXP, G_FEXP10});
+  auto &LogOps =
+      getActionDefinitionsBuilder({G_FLOG, G_FLOG10, G_FEXP, G_FEXP10});
   LogOps.customFor({S32, S16});
   LogOps.clampScalar(0, MinScalarFPTy, S32)
         .scalarize(0);

``````````

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https://github.com/llvm/llvm-project/pull/65860


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