[llvm] [AArch64][GlobalISel] Legalize G_VECREDUCE_{MIN/MAX} (PR #69461)

[David Green via llvm-commits]

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@@ -6663,6 +6663,42 @@ defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
           (UMINPv2i32 V64:$Rn, V64:$Rn)>;
 
+// For vecreduce_{opc}
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davemgreen wrote:

Can you add a comment explaining that these patterns are used by GlobalISel. It's a bit of a shame that we can't get SDAG to use the same nodes, but the return types can make that awkward. It works nicer in GlobalISel where we can opt for the return type to be in a FPR.

https://github.com/llvm/llvm-project/pull/69461