[llvm] [AMDGPU] Remove dom tree requirements from SIWholeQuadMode pass (PR #71012)
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Wed Nov 1 20:28:27 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Carl Ritson (perlfu)
<details>
<summary>Changes</summary>
SIWholeQuadMode preserves dominator and post dominator trees, but does not require them.
---
Full diff: https://github.com/llvm/llvm-project/pull/71012.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp (+2-4)
- (modified) llvm/test/CodeGen/AMDGPU/llc-pipeline.ll (-5)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 3143d437e37091b..d1d828bfbdb70da 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -238,9 +238,7 @@ class SIWholeQuadMode : public MachineFunctionPass {
AU.addRequired<LiveIntervals>();
AU.addPreserved<SlotIndexes>();
AU.addPreserved<LiveIntervals>();
- AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>();
- AU.addRequired<MachinePostDominatorTree>();
AU.addPreserved<MachinePostDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -1594,8 +1592,8 @@ bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
TRI = &TII->getRegisterInfo();
MRI = &MF.getRegInfo();
LIS = &getAnalysis<LiveIntervals>();
- MDT = &getAnalysis<MachineDominatorTree>();
- PDT = &getAnalysis<MachinePostDominatorTree>();
+ MDT = getAnalysisIfAvailable<MachineDominatorTree>();
+ PDT = getAnalysisIfAvailable<MachinePostDominatorTree>();
if (ST->isWave32()) {
AndOpc = AMDGPU::S_AND_B32;
diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index bf2f6e983b529f8..5e922f608c1daa7 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -105,7 +105,6 @@
; GCN-O0-NEXT: MachineDominator Tree Construction
; GCN-O0-NEXT: Slot index numbering
; GCN-O0-NEXT: Live Interval Analysis
-; GCN-O0-NEXT: MachinePostDominator Tree Construction
; GCN-O0-NEXT: SI Whole Quad Mode
; GCN-O0-NEXT: Virtual Register Map
; GCN-O0-NEXT: Live Register Matrix
@@ -334,7 +333,6 @@
; GCN-O1-NEXT: Register Coalescer
; GCN-O1-NEXT: Rename Disconnected Subregister Components
; GCN-O1-NEXT: Machine Instruction Scheduler
-; GCN-O1-NEXT: MachinePostDominator Tree Construction
; GCN-O1-NEXT: SI Whole Quad Mode
; GCN-O1-NEXT: Virtual Register Map
; GCN-O1-NEXT: Live Register Matrix
@@ -626,7 +624,6 @@
; GCN-O1-OPTS-NEXT: Rename Disconnected Subregister Components
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations
; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler
-; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
; GCN-O1-OPTS-NEXT: SI Whole Quad Mode
; GCN-O1-OPTS-NEXT: Virtual Register Map
; GCN-O1-OPTS-NEXT: Live Register Matrix
@@ -929,7 +926,6 @@
; GCN-O2-NEXT: Rename Disconnected Subregister Components
; GCN-O2-NEXT: AMDGPU Pre-RA optimizations
; GCN-O2-NEXT: Machine Instruction Scheduler
-; GCN-O2-NEXT: MachinePostDominator Tree Construction
; GCN-O2-NEXT: SI Whole Quad Mode
; GCN-O2-NEXT: Virtual Register Map
; GCN-O2-NEXT: Live Register Matrix
@@ -1245,7 +1241,6 @@
; GCN-O3-NEXT: Rename Disconnected Subregister Components
; GCN-O3-NEXT: AMDGPU Pre-RA optimizations
; GCN-O3-NEXT: Machine Instruction Scheduler
-; GCN-O3-NEXT: MachinePostDominator Tree Construction
; GCN-O3-NEXT: SI Whole Quad Mode
; GCN-O3-NEXT: Virtual Register Map
; GCN-O3-NEXT: Live Register Matrix
``````````
</details>
https://github.com/llvm/llvm-project/pull/71012
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