[llvm] cfb791a - [RISCV] Add RV64 i32 patterns for bseti/bclri/binvi.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 1 14:09:14 PDT 2023
Author: Craig Topper
Date: 2023-11-01T13:30:47-07:00
New Revision: cfb791aa4bb9667d60c27ff889bd5cbe8e19c806
URL: https://github.com/llvm/llvm-project/commit/cfb791aa4bb9667d60c27ff889bd5cbe8e19c806
DIFF: https://github.com/llvm/llvm-project/commit/cfb791aa4bb9667d60c27ff889bd5cbe8e19c806.diff
LOG: [RISCV] Add RV64 i32 patterns for bseti/bclri/binvi.
Needed for -riscv-experimental-rv64-legal-i32 and probably GISel.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 2579d13b59a3cb6..0a19d3542d7b130 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -817,6 +817,13 @@ def : PatGprGpr<int_riscv_xperm8, XPERM8>;
// Experimental RV64 i32 legalization patterns.
//===----------------------------------------------------------------------===//
+def BCLRMaski32 : ImmLeaf<i32, [{
+ return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
+}]>;
+def SingleBitSetMaski32 : ImmLeaf<i32, [{
+ return !isInt<12>(Imm) && isPowerOf2_32(Imm);
+}]>;
+
let Predicates = [HasStdExtZbb, IsRV64] in {
def : PatGpr<ctlz, CLZW, i32>;
def : PatGpr<cttz, CTZW, i32>;
@@ -842,3 +849,12 @@ def : Pat<(i32 (rotl GPR:$rs1, uimm5:$rs2)),
let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
}
+
+let Predicates = [HasStdExtZbs, IsRV64] in {
+def : Pat<(i32 (and GPR:$rs1, BCLRMaski32:$mask)),
+ (BCLRI GPR:$rs1, (i64 (BCLRXForm $mask)))>;
+def : Pat<(i32 (or GPR:$rs1, SingleBitSetMaski32:$mask)),
+ (BSETI GPR:$rs1, (i64 (SingleBitSetMaskToIndex $mask)))>;
+def : Pat<(i32 (xor GPR:$rs1, SingleBitSetMaski32:$mask)),
+ (BINVI GPR:$rs1, (i64 (SingleBitSetMaskToIndex $mask)))>;
+} // Predicates = [HasStdExtZbs, IsRV64]
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
index b0b75dde02231cc..0dfa56d4a00595b 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
@@ -440,34 +440,50 @@ define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
}
define signext i32 @bclri_i32_11(i32 signext %a) nounwind {
-; CHECK-LABEL: bclri_i32_11:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 1048575
-; CHECK-NEXT: addiw a1, a1, 2047
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: bclri_i32_11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: bclri_i32_11:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: bclri a0, a0, 11
+; RV64ZBS-NEXT: ret
%and = and i32 %a, -2049
ret i32 %and
}
define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
-; CHECK-LABEL: bclri_i32_30:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 786432
-; CHECK-NEXT: addiw a1, a1, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: bclri_i32_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 786432
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: bclri_i32_30:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: bclri a0, a0, 30
+; RV64ZBS-NEXT: ret
%and = and i32 %a, -1073741825
ret i32 %and
}
define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
-; CHECK-LABEL: bclri_i32_31:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 524288
-; CHECK-NEXT: addiw a1, a1, -1
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: bclri_i32_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: bclri_i32_31:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: bclri a0, a0, 31
+; RV64ZBS-NEXT: sext.w a0, a0
+; RV64ZBS-NEXT: ret
%and = and i32 %a, -2147483649
ret i32 %and
}
@@ -614,29 +630,39 @@ define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
;
; RV64ZBS-LABEL: bseti_i32_11:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bseti a1, zero, 11
-; RV64ZBS-NEXT: or a0, a0, a1
+; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret
%or = or i32 %a, 2048
ret i32 %or
}
define signext i32 @bseti_i32_30(i32 signext %a) nounwind {
-; CHECK-LABEL: bseti_i32_30:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 262144
-; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: bseti_i32_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 262144
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: bseti_i32_30:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: bseti a0, a0, 30
+; RV64ZBS-NEXT: ret
%or = or i32 %a, 1073741824
ret i32 %or
}
define signext i32 @bseti_i32_31(i32 signext %a) nounwind {
-; CHECK-LABEL: bseti_i32_31:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 524288
-; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: bseti_i32_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: bseti_i32_31:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: bseti a0, a0, 31
+; RV64ZBS-NEXT: sext.w a0, a0
+; RV64ZBS-NEXT: ret
%or = or i32 %a, 2147483648
ret i32 %or
}
@@ -748,29 +774,39 @@ define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
;
; RV64ZBS-LABEL: binvi_i32_11:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bseti a1, zero, 11
-; RV64ZBS-NEXT: xor a0, a0, a1
+; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2048
ret i32 %xor
}
define signext i32 @binvi_i32_30(i32 signext %a) nounwind {
-; CHECK-LABEL: binvi_i32_30:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 262144
-; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: binvi_i32_30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 262144
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: binvi_i32_30:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: binvi a0, a0, 30
+; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 1073741824
ret i32 %xor
}
define signext i32 @binvi_i32_31(i32 signext %a) nounwind {
-; CHECK-LABEL: binvi_i32_31:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, 524288
-; CHECK-NEXT: xor a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: binvi_i32_31:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: binvi_i32_31:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: binvi a0, a0, 31
+; RV64ZBS-NEXT: sext.w a0, a0
+; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2147483648
ret i32 %xor
}
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