[llvm] c4649d0 - [RISCV] Teach RISCVOptWInstrs that 'bset x0, 30-0' satisfies isSignExtendingOpW.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-11-01T12:29:37-07:00
New Revision: c4649d05cfc216da87868f818b2c04e78cf756e0

URL: https://github.com/llvm/llvm-project/commit/c4649d05cfc216da87868f818b2c04e78cf756e0
DIFF: https://github.com/llvm/llvm-project/commit/c4649d05cfc216da87868f818b2c04e78cf756e0.diff

LOG: [RISCV] Teach RISCVOptWInstrs that 'bset x0, 30-0' satisfies isSignExtendingOpW.

Constant materialization can use bset x0, 11 to create 2048.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index a62c7b4bbae0621..e73cab58d7016f4 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -359,6 +359,10 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
   // An ORI with an >11 bit immediate (negative 12-bit) will set bits 63:11.
   case RISCV::ORI:
     return !isUInt<11>(MI.getOperand(2).getImm());
+  // A bseti with X0 is sign extended if the immediate is less than 31.
+  case RISCV::BSETI:
+    return MI.getOperand(2).getImm() < 31 &&
+           MI.getOperand(1).getReg() == RISCV::X0;
   // Copying from X0 produces zero.
   case RISCV::COPY:
     return MI.getOperand(1).getReg() == RISCV::X0;

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
index 302b1380b9c45c9..b0b75dde02231cc 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
@@ -616,7 +616,6 @@ define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a1, zero, 11
 ; RV64ZBS-NEXT:    or a0, a0, a1
-; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %or = or i32 %a, 2048
   ret i32 %or
@@ -751,7 +750,6 @@ define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bseti a1, zero, 11
 ; RV64ZBS-NEXT:    xor a0, a0, a1
-; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %xor = xor i32 %a, 2048
   ret i32 %xor