[llvm] 5570d32 - [RISCV] Don't promote i32 and/or/xor with -riscv-experimental-rv64-legal-i32.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 1 11:38:40 PDT 2023
Author: Craig Topper
Date: 2023-11-01T11:36:46-07:00
New Revision: 5570d3250fc3212ad63e9514d1ebac76e75f7ba5
URL: https://github.com/llvm/llvm-project/commit/5570d3250fc3212ad63e9514d1ebac76e75f7ba5
DIFF: https://github.com/llvm/llvm-project/commit/5570d3250fc3212ad63e9514d1ebac76e75f7ba5.diff
LOG: [RISCV] Don't promote i32 and/or/xor with -riscv-experimental-rv64-legal-i32.
Some test improvements, but also some regressions that need to be
fixed.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVGISel.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 458bf9a2efde4d6..887671ecb435d2e 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -81,20 +81,9 @@ def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
(ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>;
let Predicates = [IsRV64] in {
-def : Pat<(i32 (and GPR:$rs1, GPR:$rs2)), (AND GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (or GPR:$rs1, GPR:$rs2)), (OR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (xor GPR:$rs1, GPR:$rs2)), (XOR GPR:$rs1, GPR:$rs2)>;
-
def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
(ADDIW GPR:$rs1, (i64 (NegImm $imm)))>;
-def : Pat<(i32 (and GPR:$rs1, simm12i32:$imm)),
- (ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
- (ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
-def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
- (XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
-
def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 67f09377bf45e48..ec5ae3e8f8d5419 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -275,16 +275,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.is64Bit()) {
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
- if (!RV64LegalI32)
+ if (!RV64LegalI32) {
setOperationAction(ISD::LOAD, MVT::i32, Custom);
-
- if (RV64LegalI32)
- setOperationAction({ISD::AND, ISD::OR, ISD::XOR}, MVT::i32, Promote);
- else
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
MVT::i32, Custom);
-
- if (!RV64LegalI32) {
setOperationAction(ISD::SADDO, MVT::i32, Custom);
setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT},
MVT::i32, Custom);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 71ba4025b6a07e9..c0a5c94835a379b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2023,12 +2023,21 @@ def : Pat<(trunc GPR:$src), (COPY GPR:$src)>;
def : PatGprGpr<add, ADDW, i32, i32>;
def : PatGprGpr<sub, SUBW, i32, i32>;
+def : PatGprGpr<and, AND, i32, i32>;
+def : PatGprGpr<or, OR, i32, i32>;
+def : PatGprGpr<xor, XOR, i32, i32>;
def : PatGprGpr<shiftopw<shl>, SLLW, i32, i64>;
def : PatGprGpr<shiftopw<srl>, SRLW, i32, i64>;
def : PatGprGpr<shiftopw<sra>, SRAW, i32, i64>;
def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
+def : Pat<(i32 (and GPR:$rs1, simm12i32:$imm)),
+ (ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
+def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
+ (ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
+def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
+ (XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
def : PatGprImm<shl, SLLIW, uimm5, i32>;
def : PatGprImm<srl, SRLIW, uimm5, i32>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index fec6396c602baad..2579d13b59a3cb6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -827,6 +827,10 @@ def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
+def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
+
def : PatGprGpr<shiftopw<rotl>, ROLW, i32, i64>;
def : PatGprGpr<shiftopw<rotr>, RORW, i32, i64>;
def : PatGprImm<rotr, RORIW, uimm5, i32>;
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
index f2228e9013ce9f1..a962a72d7037339 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
@@ -184,14 +184,14 @@ define i8 @udiv8_constant(i8 %a) nounwind {
define i8 @udiv8_pow2(i8 %a) nounwind {
; RV64I-LABEL: udiv8_pow2:
; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 248
-; RV64I-NEXT: srliw a0, a0, 3
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: srli a0, a0, 59
; RV64I-NEXT: ret
;
; RV64IM-LABEL: udiv8_pow2:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: andi a0, a0, 248
-; RV64IM-NEXT: srliw a0, a0, 3
+; RV64IM-NEXT: slli a0, a0, 56
+; RV64IM-NEXT: srli a0, a0, 59
; RV64IM-NEXT: ret
%1 = udiv i8 %a, 8
ret i8 %1
@@ -260,11 +260,10 @@ define i16 @udiv16_constant(i16 %a) nounwind {
;
; RV64IM-LABEL: udiv16_constant:
; RV64IM: # %bb.0:
+; RV64IM-NEXT: lui a1, 52429
+; RV64IM-NEXT: slli a1, a1, 4
; RV64IM-NEXT: slli a0, a0, 48
-; RV64IM-NEXT: srli a0, a0, 48
-; RV64IM-NEXT: lui a1, 13
-; RV64IM-NEXT: addi a1, a1, -819
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulhu a0, a0, a1
; RV64IM-NEXT: srliw a0, a0, 18
; RV64IM-NEXT: ret
%1 = udiv i16 %a, 5
@@ -275,15 +274,13 @@ define i16 @udiv16_pow2(i16 %a) nounwind {
; RV64I-LABEL: udiv16_pow2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
-; RV64I-NEXT: srliw a0, a0, 3
+; RV64I-NEXT: srli a0, a0, 51
; RV64I-NEXT: ret
;
; RV64IM-LABEL: udiv16_pow2:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
-; RV64IM-NEXT: srli a0, a0, 48
-; RV64IM-NEXT: srliw a0, a0, 3
+; RV64IM-NEXT: srli a0, a0, 51
; RV64IM-NEXT: ret
%1 = udiv i16 %a, 8
ret i16 %1
@@ -304,8 +301,9 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind {
;
; RV64IM-LABEL: udiv16_constant_lhs:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a0, a0, 48
-; RV64IM-NEXT: srli a0, a0, 48
+; RV64IM-NEXT: lui a1, 16
+; RV64IM-NEXT: addi a1, a1, -1
+; RV64IM-NEXT: and a0, a0, a1
; RV64IM-NEXT: li a1, 10
; RV64IM-NEXT: divuw a0, a1, a0
; RV64IM-NEXT: ret
@@ -536,8 +534,8 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV64IM-NEXT: li a1, 103
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: sraiw a1, a0, 9
-; RV64IM-NEXT: srliw a0, a0, 15
-; RV64IM-NEXT: andi a0, a0, 1
+; RV64IM-NEXT: slli a0, a0, 48
+; RV64IM-NEXT: srli a0, a0, 63
; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: ret
%1 = sdiv i8 %a, 5
@@ -549,8 +547,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 24
; RV64I-NEXT: sraiw a1, a1, 24
-; RV64I-NEXT: srliw a1, a1, 12
-; RV64I-NEXT: andi a1, a1, 7
+; RV64I-NEXT: slli a1, a1, 49
+; RV64I-NEXT: srli a1, a1, 61
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: sraiw a0, a0, 27
@@ -560,8 +558,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 24
; RV64IM-NEXT: sraiw a1, a1, 24
-; RV64IM-NEXT: srliw a1, a1, 12
-; RV64IM-NEXT: andi a1, a1, 7
+; RV64IM-NEXT: slli a1, a1, 49
+; RV64IM-NEXT: srli a1, a1, 61
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 24
; RV64IM-NEXT: sraiw a0, a0, 27
@@ -653,8 +651,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: sraiw a1, a1, 16
-; RV64I-NEXT: srliw a1, a1, 28
-; RV64I-NEXT: andi a1, a1, 7
+; RV64I-NEXT: slli a1, a1, 33
+; RV64I-NEXT: srli a1, a1, 61
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a0, a0, 16
; RV64I-NEXT: sraiw a0, a0, 19
@@ -664,8 +662,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 16
; RV64IM-NEXT: sraiw a1, a1, 16
-; RV64IM-NEXT: srliw a1, a1, 28
-; RV64IM-NEXT: andi a1, a1, 7
+; RV64IM-NEXT: slli a1, a1, 33
+; RV64IM-NEXT: srli a1, a1, 61
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 16
; RV64IM-NEXT: sraiw a0, a0, 19
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
index 11adbbdd245f1d0..292c1d8087c5362 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
@@ -330,8 +330,9 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
;
; RV64IM-LABEL: urem16_constant_lhs:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: slli a0, a0, 48
-; RV64IM-NEXT: srli a0, a0, 48
+; RV64IM-NEXT: lui a1, 16
+; RV64IM-NEXT: addi a1, a1, -1
+; RV64IM-NEXT: and a0, a0, a1
; RV64IM-NEXT: li a1, 10
; RV64IM-NEXT: remuw a0, a1, a0
; RV64IM-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
index bb2f2b73d4a0c7d..ef505afc2d1d260 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
@@ -238,10 +238,10 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: th.extu a1, a0, 31, 0
; RV64XTHEADBB-NEXT: th.ff1 a1, a1
-; RV64XTHEADBB-NEXT: addi a1, a1, -32
+; RV64XTHEADBB-NEXT: addiw a1, a1, -32
; RV64XTHEADBB-NEXT: xori a1, a1, 31
; RV64XTHEADBB-NEXT: snez a0, a0
-; RV64XTHEADBB-NEXT: addi a0, a0, -1
+; RV64XTHEADBB-NEXT: addiw a0, a0, -1
; RV64XTHEADBB-NEXT: or a0, a0, a1
; RV64XTHEADBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
@@ -749,8 +749,9 @@ define i64 @no_sexth_i64(i64 %a) nounwind {
define i32 @zexth_i32(i32 %a) nounwind {
; RV64I-LABEL: zexth_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64XTHEADBB-LABEL: zexth_i32:
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
index e6e9829c16f22b8..39a5b9b0f3676c3 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
@@ -71,16 +71,11 @@ define i64 @orn_i64(i64 %a, i64 %b) nounwind {
}
define signext i32 @xnor_i32(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: xnor_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: ret
-;
-; RV64ZBB-ZBKB-LABEL: xnor_i32:
-; RV64ZBB-ZBKB: # %bb.0:
-; RV64ZBB-ZBKB-NEXT: xnor a0, a0, a1
-; RV64ZBB-ZBKB-NEXT: ret
+; CHECK-LABEL: xnor_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xor a0, a0, a1
+; CHECK-NEXT: not a0, a0
+; CHECK-NEXT: ret
%neg = xor i32 %a, -1
%xor = xor i32 %neg, %b
ret i32 %xor
@@ -446,8 +441,8 @@ define i64 @not_shl_one_i64(i64 %x) {
define i8 @srli_i8(i8 %a) nounwind {
; CHECK-LABEL: srli_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: andi a0, a0, 192
-; CHECK-NEXT: srliw a0, a0, 6
+; CHECK-NEXT: slli a0, a0, 56
+; CHECK-NEXT: srli a0, a0, 62
; CHECK-NEXT: ret
%1 = lshr i8 %a, 6
ret i8 %1
@@ -480,25 +475,11 @@ define i8 @srai_i8(i8 %a) nounwind {
; We could use zext.h+srli, but slli+srli offers more opportunities for
; comppressed instructions.
define i16 @srli_i16(i16 %a) nounwind {
-; RV64I-LABEL: srli_i16:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
-; RV64I-NEXT: srliw a0, a0, 6
-; RV64I-NEXT: ret
-;
-; RV64ZBB-LABEL: srli_i16:
-; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: zext.h a0, a0
-; RV64ZBB-NEXT: srliw a0, a0, 6
-; RV64ZBB-NEXT: ret
-;
-; RV64ZBKB-LABEL: srli_i16:
-; RV64ZBKB: # %bb.0:
-; RV64ZBKB-NEXT: slli a0, a0, 48
-; RV64ZBKB-NEXT: srli a0, a0, 48
-; RV64ZBKB-NEXT: srliw a0, a0, 6
-; RV64ZBKB-NEXT: ret
+; CHECK-LABEL: srli_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 48
+; CHECK-NEXT: srli a0, a0, 54
+; CHECK-NEXT: ret
%1 = lshr i16 %a, 6
ret i16 %1
}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
index acc175186b85863..695ddd6d308ecbe 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
@@ -944,13 +944,16 @@ define i64 @abs_i64(i64 %x) {
define i32 @zexth_i32(i32 %a) nounwind {
; RV64I-LABEL: zexth_i32:
; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: zexth_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: zext.h a0, a0
+; RV64ZBB-NEXT: lui a1, 16
+; RV64ZBB-NEXT: addiw a1, a1, -1
+; RV64ZBB-NEXT: and a0, a0, a1
; RV64ZBB-NEXT: ret
%and = and i32 %a, 65535
ret i32 %and
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
index c4680a5e15120f6..302b1380b9c45c9 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
@@ -273,7 +273,8 @@ define signext i32 @bext_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBS-LABEL: bext_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
-; RV64ZBS-NEXT: bext a0, a0, a1
+; RV64ZBS-NEXT: srl a0, a0, a1
+; RV64ZBS-NEXT: andi a0, a0, 1
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shr = lshr i32 %a, %and
@@ -290,7 +291,8 @@ define signext i32 @bext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBS-LABEL: bext_i32_no_mask:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bext a0, a0, a1
+; RV64ZBS-NEXT: srl a0, a0, a1
+; RV64ZBS-NEXT: andi a0, a0, 1
; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, %b
%and1 = and i32 %shr, 1
@@ -367,11 +369,17 @@ define i64 @bext_i64_no_mask(i64 %a, i64 %b) nounwind {
}
define signext i32 @bexti_i32(i32 signext %a) nounwind {
-; CHECK-LABEL: bexti_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: srliw a0, a0, 5
-; CHECK-NEXT: andi a0, a0, 1
-; CHECK-NEXT: ret
+; RV64I-LABEL: bexti_i32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 58
+; RV64I-NEXT: srli a0, a0, 63
+; RV64I-NEXT: ret
+;
+; RV64ZBS-LABEL: bexti_i32:
+; RV64ZBS: # %bb.0:
+; RV64ZBS-NEXT: srliw a0, a0, 5
+; RV64ZBS-NEXT: andi a0, a0, 1
+; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, 5
%and = and i32 %shr, 1
ret i32 %and
@@ -394,16 +402,11 @@ define i64 @bexti_i64(i64 %a) nounwind {
}
define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
-; RV64I-LABEL: bexti_i32_cmp:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 58
-; RV64I-NEXT: srli a0, a0, 63
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: bexti_i32_cmp:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bexti a0, a0, 5
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: bexti_i32_cmp:
+; CHECK: # %bb.0:
+; CHECK-NEXT: andi a0, a0, 32
+; CHECK-NEXT: snez a0, a0
+; CHECK-NEXT: ret
%and = and i32 %a, 32
%cmp = icmp ne i32 %and, 0
%zext = zext i1 %cmp to i32
@@ -437,33 +440,23 @@ define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
}
define signext i32 @bclri_i32_11(i32 signext %a) nounwind {
-; RV64I-LABEL: bclri_i32_11:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 1048575
-; RV64I-NEXT: addiw a1, a1, 2047
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: bclri_i32_11:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bclri a0, a0, 11
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: bclri_i32_11:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 1048575
+; CHECK-NEXT: addiw a1, a1, 2047
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: ret
%and = and i32 %a, -2049
ret i32 %and
}
define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
-; RV64I-LABEL: bclri_i32_30:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 786432
-; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: bclri_i32_30:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bclri a0, a0, 30
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: bclri_i32_30:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 786432
+; CHECK-NEXT: addiw a1, a1, -1
+; CHECK-NEXT: and a0, a0, a1
+; CHECK-NEXT: ret
%and = and i32 %a, -1073741825
ret i32 %and
}
@@ -471,8 +464,9 @@ define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: bclri_i32_31:
; CHECK: # %bb.0:
-; CHECK-NEXT: slli a0, a0, 33
-; CHECK-NEXT: srli a0, a0, 33
+; CHECK-NEXT: lui a1, 524288
+; CHECK-NEXT: addiw a1, a1, -1
+; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: ret
%and = and i32 %a, -2147483649
ret i32 %and
@@ -614,29 +608,26 @@ define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: bseti_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
-; RV64I-NEXT: slli a1, a1, 11
+; RV64I-NEXT: slliw a1, a1, 11
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i32_11:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bseti a0, a0, 11
+; RV64ZBS-NEXT: bseti a1, zero, 11
+; RV64ZBS-NEXT: or a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%or = or i32 %a, 2048
ret i32 %or
}
define signext i32 @bseti_i32_30(i32 signext %a) nounwind {
-; RV64I-LABEL: bseti_i32_30:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 262144
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: bseti_i32_30:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: bseti a0, a0, 30
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: bseti_i32_30:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 262144
+; CHECK-NEXT: or a0, a0, a1
+; CHECK-NEXT: ret
%or = or i32 %a, 1073741824
ret i32 %or
}
@@ -752,29 +743,26 @@ define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: binvi_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
-; RV64I-NEXT: slli a1, a1, 11
+; RV64I-NEXT: slliw a1, a1, 11
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i32_11:
; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: binvi a0, a0, 11
+; RV64ZBS-NEXT: bseti a1, zero, 11
+; RV64ZBS-NEXT: xor a0, a0, a1
+; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2048
ret i32 %xor
}
define signext i32 @binvi_i32_30(i32 signext %a) nounwind {
-; RV64I-LABEL: binvi_i32_30:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 262144
-; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: ret
-;
-; RV64ZBS-LABEL: binvi_i32_30:
-; RV64ZBS: # %bb.0:
-; RV64ZBS-NEXT: binvi a0, a0, 30
-; RV64ZBS-NEXT: ret
+; CHECK-LABEL: binvi_i32_30:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a1, 262144
+; CHECK-NEXT: xor a0, a0, a1
+; CHECK-NEXT: ret
%xor = xor i32 %a, 1073741824
ret i32 %xor
}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
index 774d1398644b984..20eb4cc10f40547 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
@@ -758,7 +758,8 @@ define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: srai a1, a0, 32
; RV64-NEXT: sraiw a0, a0, 31
; RV64-NEXT: xor a0, a1, a0
-; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
entry:
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -792,7 +793,8 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: xor a0, a2, a0
-; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -827,7 +829,8 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: mulhu a0, a0, a1
; RV64-NEXT: srai a0, a0, 32
-; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -856,7 +859,8 @@ define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
; RV64-LABEL: umulo.not.i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a0, a0, a1
-; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: xori a0, a0, 1
; RV64-NEXT: ret
entry:
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
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