[llvm] 7a5c14c - [X86] Regenerate test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 1 08:37:38 PDT 2023
Author: Nikita Popov
Date: 2023-11-01T16:37:30+01:00
New Revision: 7a5c14cb275e10d8ecef156d8c3273b3f2a74abe
URL: https://github.com/llvm/llvm-project/commit/7a5c14cb275e10d8ecef156d8c3273b3f2a74abe
DIFF: https://github.com/llvm/llvm-project/commit/7a5c14cb275e10d8ecef156d8c3273b3f2a74abe.diff
LOG: [X86] Regenerate test checks (NFC)
Added:
Modified:
llvm/test/CodeGen/X86/codegen-prepare-extload.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll
index 6695576c557aa5e..f835d4f2dbad70f 100644
--- a/llvm/test/CodeGen/X86/codegen-prepare-extload.ll
+++ b/llvm/test/CodeGen/X86/codegen-prepare-extload.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win64 | FileCheck %s
; RUN: opt -codegenprepare < %s -mtriple=x86_64-apple-macosx -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS
@@ -10,13 +11,20 @@
;
; CHECK-LABEL: foo:
; CHECK: movsbl ({{%rdi|%rcx}}), %eax
-;
-; OPTALL-LABEL: @foo
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; OPTALL: store i32 [[ZEXT]], ptr %q
-; OPTALL: ret
define void @foo(ptr %p, ptr %q) {
+; OPTALL-LABEL: define void @foo(
+; OPTALL-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
+; OPTALL-NEXT: entry:
+; OPTALL-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; OPTALL-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
+; OPTALL-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; OPTALL-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; OPTALL: true:
+; OPTALL-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; OPTALL-NEXT: ret void
+; OPTALL: false:
+; OPTALL-NEXT: ret void
+;
entry:
%t = load i8, ptr %p
%a = icmp slt i8 %t, 20
@@ -31,16 +39,36 @@ false:
; Check that we manage to form a zextload is an operation with only one
; argument to explicitly extend is in the way.
-; OPTALL-LABEL: @promoteOneArg
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
; Make sure the operation is not promoted when the promotion pass is disabled.
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
define void @promoteOneArg(ptr %p, ptr %q) {
+; OPT-LABEL: define void @promoteOneArg(
+; OPT-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
+; OPT-NEXT: entry:
+; OPT-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; OPT-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
+; OPT-NEXT: [[ADD:%.*]] = add nuw i32 [[S]], 2
+; OPT-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; OPT-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; OPT: true:
+; OPT-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; OPT-NEXT: ret void
+; OPT: false:
+; OPT-NEXT: ret void
+;
+; DISABLE-LABEL: define void @promoteOneArg(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[ADD:%.*]] = add nuw i8 [[T]], 2
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
+;
entry:
%t = load i8, ptr %p
%add = add nuw i8 %t, 2
@@ -57,15 +85,35 @@ false:
; Check that we manage to form a sextload is an operation with only one
; argument to explicitly extend is in the way.
; Version with sext.
-; OPTALL-LABEL: @promoteOneArgSExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
-; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
define void @promoteOneArgSExt(ptr %p, ptr %q) {
+; OPT-LABEL: define void @promoteOneArgSExt(
+; OPT-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
+; OPT-NEXT: entry:
+; OPT-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; OPT-NEXT: [[S:%.*]] = sext i8 [[T]] to i32
+; OPT-NEXT: [[ADD:%.*]] = add nsw i32 [[S]], 2
+; OPT-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; OPT-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; OPT: true:
+; OPT-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; OPT-NEXT: ret void
+; OPT: false:
+; OPT-NEXT: ret void
+;
+; DISABLE-LABEL: define void @promoteOneArgSExt(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[ADD:%.*]] = add nsw i8 [[T]], 2
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = sext i8 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
+;
entry:
%t = load i8, ptr %p
%add = add nsw i8 %t, 2
@@ -87,24 +135,51 @@ false:
; #1 will not be removed as we do not know anything about %b.
; #2 may not be merged with the load because %t is used in a comparison.
; Since two extensions may be emitted in the end instead of one before the
-; transformation, the regular heuristic does not apply the optimization.
-;
-; OPTALL-LABEL: @promoteTwoArgZext
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-;
-; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
-; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
+; transformation, the regular heuristic does not apply the optimization.
+define void @promoteTwoArgZext(ptr %p, ptr %q, i8 %b) {
+; NONSTRESS-LABEL: define void @promoteTwoArgZext(
+; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
+; NONSTRESS-NEXT: entry:
+; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; NONSTRESS-NEXT: [[ADD:%.*]] = add nuw i8 [[T]], [[B]]
+; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; NONSTRESS: true:
+; NONSTRESS-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
+; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; NONSTRESS-NEXT: ret void
+; NONSTRESS: false:
+; NONSTRESS-NEXT: ret void
;
-; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
-; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+; STRESS-LABEL: define void @promoteTwoArgZext(
+; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
+; STRESS-NEXT: entry:
+; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; STRESS-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
+; STRESS-NEXT: [[PROMOTED:%.*]] = zext i8 [[B]] to i32
+; STRESS-NEXT: [[ADD:%.*]] = add nuw i32 [[S]], [[PROMOTED]]
+; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; STRESS: true:
+; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; STRESS-NEXT: ret void
+; STRESS: false:
+; STRESS-NEXT: ret void
;
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+; DISABLE-LABEL: define void @promoteTwoArgZext(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[ADD:%.*]] = add nuw i8 [[T]], [[B]]
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
;
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
-define void @promoteTwoArgZext(ptr %p, ptr %q, i8 %b) {
entry:
%t = load i8, ptr %p
%add = add nuw i8 %t, %b
@@ -121,21 +196,50 @@ false:
; Check that we manage to form a sextload is an operation with two
; arguments to explicitly extend is in the way.
; Version with sext.
-; OPTALL-LABEL: @promoteTwoArgSExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
+define void @promoteTwoArgSExt(ptr %p, ptr %q, i8 %b) {
+; NONSTRESS-LABEL: define void @promoteTwoArgSExt(
+; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
+; NONSTRESS-NEXT: entry:
+; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; NONSTRESS-NEXT: [[ADD:%.*]] = add nsw i8 [[T]], [[B]]
+; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; NONSTRESS: true:
+; NONSTRESS-NEXT: [[S:%.*]] = sext i8 [[ADD]] to i32
+; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; NONSTRESS-NEXT: ret void
+; NONSTRESS: false:
+; NONSTRESS-NEXT: ret void
;
-; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
-; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32
-; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXTLD]], [[SEXTB]]
+; STRESS-LABEL: define void @promoteTwoArgSExt(
+; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
+; STRESS-NEXT: entry:
+; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; STRESS-NEXT: [[S:%.*]] = sext i8 [[T]] to i32
+; STRESS-NEXT: [[PROMOTED:%.*]] = sext i8 [[B]] to i32
+; STRESS-NEXT: [[ADD:%.*]] = add nsw i32 [[S]], [[PROMOTED]]
+; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; STRESS: true:
+; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; STRESS-NEXT: ret void
+; STRESS: false:
+; STRESS-NEXT: ret void
;
-; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
-; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
+; DISABLE-LABEL: define void @promoteTwoArgSExt(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[ADD:%.*]] = add nsw i8 [[T]], [[B]]
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = sext i8 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
;
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
-define void @promoteTwoArgSExt(ptr %p, ptr %q, i8 %b) {
entry:
%t = load i8, ptr %p
%add = add nsw i8 %t, %b
@@ -151,26 +255,54 @@ false:
; Check that we do not a zextload if we need to introduce more than
; one additional extension.
-; OPTALL-LABEL: @promoteThreeArgZext
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-;
-; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32
-; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
-; STRESS-NEXT: [[ZEXTC:%[a-zA-Z_0-9-]+]] = zext i8 %c to i32
-; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]]
+define void @promoteThreeArgZext(ptr %p, ptr %q, i8 %b, i8 %c) {
+; NONSTRESS-LABEL: define void @promoteThreeArgZext(
+; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
+; NONSTRESS-NEXT: entry:
+; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; NONSTRESS-NEXT: [[TMP:%.*]] = add nuw i8 [[T]], [[B]]
+; NONSTRESS-NEXT: [[ADD:%.*]] = add nuw i8 [[TMP]], [[C]]
+; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; NONSTRESS: true:
+; NONSTRESS-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
+; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; NONSTRESS-NEXT: ret void
+; NONSTRESS: false:
+; NONSTRESS-NEXT: ret void
;
-; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b
-; NONSTRESS-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[TMP]], %c
-; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+; STRESS-LABEL: define void @promoteThreeArgZext(
+; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
+; STRESS-NEXT: entry:
+; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; STRESS-NEXT: [[S:%.*]] = zext i8 [[T]] to i32
+; STRESS-NEXT: [[PROMOTED1:%.*]] = zext i8 [[B]] to i32
+; STRESS-NEXT: [[TMP:%.*]] = add nuw i32 [[S]], [[PROMOTED1]]
+; STRESS-NEXT: [[PROMOTED:%.*]] = zext i8 [[C]] to i32
+; STRESS-NEXT: [[ADD:%.*]] = add nuw i32 [[TMP]], [[PROMOTED]]
+; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; STRESS: true:
+; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; STRESS-NEXT: ret void
+; STRESS: false:
+; STRESS-NEXT: ret void
;
-; DISABLE: add nuw i8
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
+; DISABLE-LABEL: define void @promoteThreeArgZext(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[TMP:%.*]] = add nuw i8 [[T]], [[B]]
+; DISABLE-NEXT: [[ADD:%.*]] = add nuw i8 [[TMP]], [[C]]
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = zext i8 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
;
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
-define void @promoteThreeArgZext(ptr %p, ptr %q, i8 %b, i8 %c) {
entry:
%t = load i8, ptr %p
%tmp = add nuw i8 %t, %b
@@ -187,24 +319,52 @@ false:
; Check that we manage to form a zextload after promoting and merging
; two extensions.
-; OPTALL-LABEL: @promoteMergeExtArgZExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-;
-; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32
-; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
+define void @promoteMergeExtArgZExt(ptr %p, ptr %q, i16 %b) {
+; NONSTRESS-LABEL: define void @promoteMergeExtArgZExt(
+; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
+; NONSTRESS-NEXT: entry:
+; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; NONSTRESS-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
+; NONSTRESS-NEXT: [[ADD:%.*]] = add nuw i16 [[EXT]], [[B]]
+; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; NONSTRESS: true:
+; NONSTRESS-NEXT: [[S:%.*]] = zext i16 [[ADD]] to i32
+; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; NONSTRESS-NEXT: ret void
+; NONSTRESS: false:
+; NONSTRESS-NEXT: ret void
;
-; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
-; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
-; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
+; STRESS-LABEL: define void @promoteMergeExtArgZExt(
+; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
+; STRESS-NEXT: entry:
+; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; STRESS-NEXT: [[PROMOTED1:%.*]] = zext i8 [[T]] to i32
+; STRESS-NEXT: [[PROMOTED:%.*]] = zext i16 [[B]] to i32
+; STRESS-NEXT: [[ADD:%.*]] = add nuw i32 [[PROMOTED1]], [[PROMOTED]]
+; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; STRESS: true:
+; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; STRESS-NEXT: ret void
+; STRESS: false:
+; STRESS-NEXT: ret void
;
-; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32
+; DISABLE-LABEL: define void @promoteMergeExtArgZExt(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
+; DISABLE-NEXT: [[ADD:%.*]] = add nuw i16 [[EXT]], [[B]]
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = zext i16 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
;
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
-define void @promoteMergeExtArgZExt(ptr %p, ptr %q, i16 %b) {
entry:
%t = load i8, ptr %p
%ext = zext i8 %t to i16
@@ -222,23 +382,52 @@ false:
; Check that we manage to form a sextload after promoting and merging
; two extensions.
; Version with sext.
-; OPTALL-LABEL: @promoteMergeExtArgSExt
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
+define void @promoteMergeExtArgSExt(ptr %p, ptr %q, i16 %b) {
+; NONSTRESS-LABEL: define void @promoteMergeExtArgSExt(
+; NONSTRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
+; NONSTRESS-NEXT: entry:
+; NONSTRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; NONSTRESS-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
+; NONSTRESS-NEXT: [[ADD:%.*]] = add nsw i16 [[EXT]], [[B]]
+; NONSTRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; NONSTRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; NONSTRESS: true:
+; NONSTRESS-NEXT: [[S:%.*]] = sext i16 [[ADD]] to i32
+; NONSTRESS-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; NONSTRESS-NEXT: ret void
+; NONSTRESS: false:
+; NONSTRESS-NEXT: ret void
;
-; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32
-; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXTLD]], [[ZEXTB]]
+; STRESS-LABEL: define void @promoteMergeExtArgSExt(
+; STRESS-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
+; STRESS-NEXT: entry:
+; STRESS-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; STRESS-NEXT: [[PROMOTED1:%.*]] = zext i8 [[T]] to i32
+; STRESS-NEXT: [[PROMOTED:%.*]] = sext i16 [[B]] to i32
+; STRESS-NEXT: [[ADD:%.*]] = add nsw i32 [[PROMOTED1]], [[PROMOTED]]
+; STRESS-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; STRESS-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; STRESS: true:
+; STRESS-NEXT: store i32 [[ADD]], ptr [[Q]], align 4
+; STRESS-NEXT: ret void
+; STRESS: false:
+; STRESS-NEXT: ret void
;
-; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
-; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
-; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
+; DISABLE-LABEL: define void @promoteMergeExtArgSExt(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i16 [[B:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[EXT:%.*]] = zext i8 [[T]] to i16
+; DISABLE-NEXT: [[ADD:%.*]] = add nsw i16 [[EXT]], [[B]]
+; DISABLE-NEXT: [[A:%.*]] = icmp slt i8 [[T]], 20
+; DISABLE-NEXT: br i1 [[A]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; DISABLE: true:
+; DISABLE-NEXT: [[S:%.*]] = sext i16 [[ADD]] to i32
+; DISABLE-NEXT: store i32 [[S]], ptr [[Q]], align 4
+; DISABLE-NEXT: ret void
+; DISABLE: false:
+; DISABLE-NEXT: ret void
;
-; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
-; OPTALL: store i32 [[RES]], ptr %q
-; OPTALL: ret
-define void @promoteMergeExtArgSExt(ptr %p, ptr %q, i16 %b) {
entry:
%t = load i8, ptr %p
%ext = zext i8 %t to i16
@@ -281,30 +470,38 @@ false:
; a zext of %ld.
; Currently we do not try to reuse existing extensions, so in the end we have
; 3 identical zext of %ld. The extensions will be CSE'ed by SDag.
+define void @severalPromotions(ptr %addr1, ptr %addr2, i8 %a, i32 %b) {
+; OPT-LABEL: define void @severalPromotions(
+; OPT-SAME: ptr [[ADDR1:%.*]], ptr [[ADDR2:%.*]], i8 [[A:%.*]], i32 [[B:%.*]]) {
+; OPT-NEXT: [[LD:%.*]] = load i8, ptr [[ADDR1]], align 1
+; OPT-NEXT: [[PROMOTED4:%.*]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[PROMOTED3:%.*]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[LD2:%.*]] = load i32, ptr [[ADDR2]], align 4
+; OPT-NEXT: [[SEXTADD:%.*]] = sext i32 [[LD2]] to i64
+; OPT-NEXT: [[PROMOTED1:%.*]] = zext i8 [[LD]] to i64
+; OPT-NEXT: [[ADD:%.*]] = add nsw i64 [[SEXTADD]], [[PROMOTED1]]
+; OPT-NEXT: [[PROMOTED2:%.*]] = zext i8 [[A]] to i64
+; OPT-NEXT: [[ADDZA:%.*]] = add nsw i64 [[PROMOTED2]], [[PROMOTED3]]
+; OPT-NEXT: [[SEXTADDB:%.*]] = sext i32 [[B]] to i64
+; OPT-NEXT: [[ADDB:%.*]] = add nsw i64 [[SEXTADDB]], [[PROMOTED4]]
+; OPT-NEXT: call void @dummy(i64 [[ADD]], i64 [[ADDZA]], i64 [[ADDB]])
+; OPT-NEXT: ret void
;
-; OPTALL-LABEL: @severalPromotions
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %addr1
-; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
-; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
-; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, ptr %addr2
-; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64
-; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
-; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_3]]
-; OPT-NEXT: [[ZEXTLD1_4:%[a-zA-Z_0-9-]+]] = zext i8 %a to i64
-; OPT-NEXT: [[RESZA:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXTLD1_4]], [[ZEXTLD1_2]]
-; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64
-; OPT-NEXT: [[RESB:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTB]], [[ZEXTLD1_1]]
-;
-; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32
-; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
-; DISABLE: [[ADDZA:%[a-zA-Z_0-9-]+]] = add nsw i32
-; DISABLE: [[RESZA:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDZA]] to i64
-; DISABLE: [[ADDB:%[a-zA-Z_0-9-]+]] = add nsw i32
-; DISABLE: [[RESB:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDB]] to i64
+; DISABLE-LABEL: define void @severalPromotions(
+; DISABLE-SAME: ptr [[ADDR1:%.*]], ptr [[ADDR2:%.*]], i8 [[A:%.*]], i32 [[B:%.*]]) {
+; DISABLE-NEXT: [[LD:%.*]] = load i8, ptr [[ADDR1]], align 1
+; DISABLE-NEXT: [[ZEXTLD:%.*]] = zext i8 [[LD]] to i32
+; DISABLE-NEXT: [[LD2:%.*]] = load i32, ptr [[ADDR2]], align 4
+; DISABLE-NEXT: [[ADD:%.*]] = add nsw i32 [[LD2]], [[ZEXTLD]]
+; DISABLE-NEXT: [[SEXTADD:%.*]] = sext i32 [[ADD]] to i64
+; DISABLE-NEXT: [[ZEXTA:%.*]] = zext i8 [[A]] to i32
+; DISABLE-NEXT: [[ADDZA:%.*]] = add nsw i32 [[ZEXTA]], [[ZEXTLD]]
+; DISABLE-NEXT: [[SEXTADDZA:%.*]] = sext i32 [[ADDZA]] to i64
+; DISABLE-NEXT: [[ADDB:%.*]] = add nsw i32 [[B]], [[ZEXTLD]]
+; DISABLE-NEXT: [[SEXTADDB:%.*]] = sext i32 [[ADDB]] to i64
+; DISABLE-NEXT: call void @dummy(i64 [[SEXTADD]], i64 [[SEXTADDZA]], i64 [[SEXTADDB]])
+; DISABLE-NEXT: ret void
;
-; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]])
-; OPTALL: ret
-define void @severalPromotions(ptr %addr1, ptr %addr2, i8 %a, i32 %b) {
%ld = load i8, ptr %addr1
%zextld = zext i8 %ld to i32
%ld2 = load i32, ptr %addr2
@@ -323,11 +520,13 @@ declare void @dummy(i64, i64, i64)
; Make sure we do not try to promote vector types since the type promotion
; helper does not support them for now.
-; OPTALL-LABEL: @vectorPromotion
-; OPTALL: [[SHL:%[a-zA-Z_0-9-]+]] = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
-; OPTALL: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext <2 x i32> [[SHL]] to <2 x i64>
-; OPTALL: ret
define void @vectorPromotion() {
+; OPTALL-LABEL: define void @vectorPromotion() {
+; OPTALL-NEXT: entry:
+; OPTALL-NEXT: [[A:%.*]] = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
+; OPTALL-NEXT: [[B:%.*]] = zext <2 x i32> [[A]] to <2 x i64>
+; OPTALL-NEXT: ret void
+;
entry:
%a = shl nuw nsw <2 x i32> zeroinitializer, <i32 8, i32 8>
%b = zext <2 x i32> %a to <2 x i64>
@@ -341,17 +540,23 @@ entry:
; Make sure we support promotion of operands that produces a Value as opposed
; to an instruction.
; This used to cause a crash.
-; OPTALL-LABEL: @promotionOfArgEndsUpInValue
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, ptr %addr
-
-; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
-; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i32)
+define i32 @promotionOfArgEndsUpInValue(ptr %addr) {
+; OPT-LABEL: define i32 @promotionOfArgEndsUpInValue(
+; OPT-SAME: ptr [[ADDR:%.*]]) {
+; OPT-NEXT: entry:
+; OPT-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 2
+; OPT-NEXT: [[CONV3:%.*]] = sext i16 [[VAL]] to i32
+; OPT-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV3]], zext (i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i32)
+; OPT-NEXT: ret i32 [[ADD]]
;
-; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], zext (i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16)
-; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32
+; DISABLE-LABEL: define i32 @promotionOfArgEndsUpInValue(
+; DISABLE-SAME: ptr [[ADDR:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[VAL:%.*]] = load i16, ptr [[ADDR]], align 2
+; DISABLE-NEXT: [[ADD:%.*]] = add nuw nsw i16 [[VAL]], zext (i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16)
+; DISABLE-NEXT: [[CONV3:%.*]] = sext i16 [[ADD]] to i32
+; DISABLE-NEXT: ret i32 [[CONV3]]
;
-; OPTALL-NEXT: ret i32 [[RES]]
-define i32 @promotionOfArgEndsUpInValue(ptr %addr) {
entry:
%val = load i16, ptr %addr
%add = add nuw nsw i16 %val, zext (i1 icmp ne (ptr getelementptr inbounds ([2 x i32], ptr @c, i64 0, i64 1), ptr @a) to i16)
@@ -360,25 +565,31 @@ entry:
}
; Check that we see that one zext can be derived from the other for free.
-; OPTALL-LABEL: @promoteTwoArgZextWithSourceExtendedTwice
-; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
-
-; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
-; OPT-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
-; OPT-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], 12
-; OPT-NEXT: store i32 [[RES32]], ptr %addr
-; OPT-NEXT: store i64 [[RES64]], ptr %q
+define void @promoteTwoArgZextWithSourceExtendedTwice(ptr %p, ptr %q, i32 %b, ptr %addr) {
+; OPT-LABEL: define void @promoteTwoArgZextWithSourceExtendedTwice(
+; OPT-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i32 [[B:%.*]], ptr [[ADDR:%.*]]) {
+; OPT-NEXT: entry:
+; OPT-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; OPT-NEXT: [[PROMOTED:%.*]] = zext i8 [[T]] to i64
+; OPT-NEXT: [[ZEXTT:%.*]] = zext i8 [[T]] to i32
+; OPT-NEXT: [[ADD:%.*]] = add nuw i32 [[ZEXTT]], [[B]]
+; OPT-NEXT: [[ADD2:%.*]] = add nuw i64 [[PROMOTED]], 12
+; OPT-NEXT: store i32 [[ADD]], ptr [[ADDR]], align 4
+; OPT-NEXT: store i64 [[ADD2]], ptr [[Q]], align 8
+; OPT-NEXT: ret void
;
-; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
-; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
-; DISABLE-NEXT: [[RES2_32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], 12
-; DISABLE-NEXT: store i32 [[RES32]], ptr %addr
-; DISABLE-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES2_32]] to i64
-; DISABLE-NEXT: store i64 [[ZEXT64]], ptr %q
+; DISABLE-LABEL: define void @promoteTwoArgZextWithSourceExtendedTwice(
+; DISABLE-SAME: ptr [[P:%.*]], ptr [[Q:%.*]], i32 [[B:%.*]], ptr [[ADDR:%.*]]) {
+; DISABLE-NEXT: entry:
+; DISABLE-NEXT: [[T:%.*]] = load i8, ptr [[P]], align 1
+; DISABLE-NEXT: [[ZEXTT:%.*]] = zext i8 [[T]] to i32
+; DISABLE-NEXT: [[ADD:%.*]] = add nuw i32 [[ZEXTT]], [[B]]
+; DISABLE-NEXT: [[ADD2:%.*]] = add nuw i32 [[ZEXTT]], 12
+; DISABLE-NEXT: store i32 [[ADD]], ptr [[ADDR]], align 4
+; DISABLE-NEXT: [[S:%.*]] = zext i32 [[ADD2]] to i64
+; DISABLE-NEXT: store i64 [[S]], ptr [[Q]], align 8
+; DISABLE-NEXT: ret void
;
-; OPTALL-NEXT: ret void
-define void @promoteTwoArgZextWithSourceExtendedTwice(ptr %p, ptr %q, i32 %b, ptr %addr) {
entry:
%t = load i8, ptr %p
%zextt = zext i8 %t to i32
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