[llvm] c449a64 - [SLP][NFC]Add the test shoing issue with -slp-vectorize-hor-store

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2023-11-01T08:31:18-07:00
New Revision: c449a64c3eb2e6bf5ad87ceb20911015f9bd4963

URL: https://github.com/llvm/llvm-project/commit/c449a64c3eb2e6bf5ad87ceb20911015f9bd4963
DIFF: https://github.com/llvm/llvm-project/commit/c449a64c3eb2e6bf5ad87ceb20911015f9bd4963.diff

LOG: [SLP][NFC]Add the test shoing issue with -slp-vectorize-hor-store
option, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/X86/horizontal-store-many-uses.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-store-many-uses.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-store-many-uses.ll
new file mode 100644
index 000000000000000..d93f1edfc5971e6
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-store-many-uses.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux | FileCheck %s
+
+ at arr_i32 = global [32 x i32] zeroinitializer, align 16
+define void @test(ptr noalias %pl, ptr noalias %res, ptr noalias %p2) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ptr noalias [[PL:%.*]], ptr noalias [[RES:%.*]], ptr noalias [[P2:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr @arr_i32, align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr_i32, i64 0, i64 1), align 4
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP0]]
+; CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr_i32, i64 0, i64 2), align 8
+; CHECK-NEXT:    [[ADD_1:%.*]] = add nsw i32 [[TMP2]], [[ADD]]
+; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr_i32, i64 0, i64 3), align 4
+; CHECK-NEXT:    [[ADD_2:%.*]] = add nsw i32 [[TMP3]], [[ADD_1]]
+; CHECK-NEXT:    store i32 [[ADD_2]], ptr [[P2]], align 16
+; CHECK-NEXT:    store i32 [[ADD_2]], ptr [[RES]], align 16
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = load i32, ptr @arr_i32, align 16
+  %1 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr_i32, i64 0, i64 1), align 4
+  %add = add nsw i32 %1, %0
+  %2 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr_i32, i64 0, i64 2), align 8
+  %add.1 = add nsw i32 %2, %add
+  %3 = load i32, ptr getelementptr inbounds ([32 x i32], ptr @arr_i32, i64 0, i64 3), align 4
+  %add.2 = add nsw i32 %3, %add.1
+  store i32 %add.2, ptr %p2, align 16
+  store i32 %add.2, ptr %res, align 16
+  ret void
+}
+