[llvm] ISel/RISCV: restrict custom lowering of ISD::LRINT, ISD::LLRINT (PR #70926)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Ramkumar Ramachandra (artagnon)

<details>
<summary>Changes</summary>

To follow up on 7a76038 (CodeGen/RISCV: increase test coverage of lrint, llrint), it is clear that the custom lowering of ISD::LRINT always works for i32, and only works for i64 if the subtarget is 64-bit. ISD::LLRINT custom-lowering works for i32 and i64. Hence, guard the appropriate setOperationAction() calls with these checks.

---
Full diff: https://github.com/llvm/llvm-project/pull/70926.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+6-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e9f80432ab190c7..479937f83cffa84 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -731,7 +731,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                          VT, Custom);
       setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT,
                          Custom);
-      setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
+      if (VT.getVectorElementType() == MVT::i32 ||
+          (VT.getVectorElementType() == MVT::i64 && Subtarget.is64Bit()))
+        setOperationAction({ISD::LRINT}, VT, Custom);
+      if (VT.getVectorElementType() == MVT::i64 ||
+          VT.getVectorElementType() == MVT::i32)
+        setOperationAction({ISD::LLRINT}, VT, Custom);
       setOperationAction(
           {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal);
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/70926