[llvm] 6930c3a - [RISCV][GISel] Make s64 G_LOAD/G_STORE legal on RV32 with D extension.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 31 23:45:21 PDT 2023


Author: Craig Topper
Date: 2023-10-31T23:40:13-07:00
New Revision: 6930c3a49bafe2d889e70452be1a1688b0ac7d28

URL: https://github.com/llvm/llvm-project/commit/6930c3a49bafe2d889e70452be1a1688b0ac7d28
DIFF: https://github.com/llvm/llvm-project/commit/6930c3a49bafe2d889e70452be1a1688b0ac7d28.diff

LOG: [RISCV][GISel] Make s64 G_LOAD/G_STORE legal on RV32 with D extension.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 2031cabc75a318e..662e5e553121c8e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -111,6 +111,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
                                                {s64, p0, s64, 64}});
     ExtLoadActions.legalForTypesWithMemDesc(
         {{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
+  } else if (ST.hasStdExtD()) {
+    LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s64, 64}});
   }
   LoadStoreActions.clampScalar(0, s32, sXLen).lower();
   ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();


        


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