[llvm] 264f5ec - [RISCV][GISel] Refactor the load/store action builder to prepare for upcoming patch. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 31 23:26:50 PDT 2023
Author: Craig Topper
Date: 2023-10-31T23:24:34-07:00
New Revision: 264f5ec99c2567c2e0ef21a39016318dc2b0da26
URL: https://github.com/llvm/llvm-project/commit/264f5ec99c2567c2e0ef21a39016318dc2b0da26
DIFF: https://github.com/llvm/llvm-project/commit/264f5ec99c2567c2e0ef21a39016318dc2b0da26.diff
LOG: [RISCV][GISel] Refactor the load/store action builder to prepare for upcoming patch. NFC
Remove redundancy from RV32 by not using sXLen in the legalization
rules. Make s64 conditional on XLen==64 instead.
Preparation for making s64 legal on RV32+D.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index e80d620936e893b..2031cabc75a318e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -95,25 +95,24 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
.clampScalar(0, sXLen, sXLen)
.clampScalar(1, sXLen, sXLen);
- getActionDefinitionsBuilder({G_LOAD, G_STORE})
- .legalForTypesWithMemDesc({{s32, p0, s8, 8},
- {s32, p0, s16, 16},
- {s32, p0, s32, 32},
- {sXLen, p0, s8, 8},
- {sXLen, p0, s16, 16},
- {sXLen, p0, s32, 32},
- {sXLen, p0, sXLen, XLen},
- {p0, p0, sXLen, XLen}})
- .clampScalar(0, s32, sXLen)
- .lower();
-
- auto &ExtLoadActions = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
- .legalForTypesWithMemDesc({{s32, p0, s8, 8},
- {s32, p0, s16, 16},
- {sXLen, p0, s8, 8},
- {sXLen, p0, s16, 16}});
- if (XLen == 64)
- ExtLoadActions.legalForTypesWithMemDesc({{sXLen, p0, s32, 32}});
+ auto &LoadStoreActions =
+ getActionDefinitionsBuilder({G_LOAD, G_STORE})
+ .legalForTypesWithMemDesc({{s32, p0, s8, 8},
+ {s32, p0, s16, 16},
+ {s32, p0, s32, 32},
+ {p0, p0, sXLen, XLen}});
+ auto &ExtLoadActions =
+ getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
+ .legalForTypesWithMemDesc({{s32, p0, s8, 8}, {s32, p0, s16, 16}});
+ if (XLen == 64) {
+ LoadStoreActions.legalForTypesWithMemDesc({{s64, p0, s8, 8},
+ {s64, p0, s16, 16},
+ {s64, p0, s32, 32},
+ {s64, p0, s64, 64}});
+ ExtLoadActions.legalForTypesWithMemDesc(
+ {{s64, p0, s8, 8}, {s64, p0, s16, 16}, {s64, p0, s32, 32}});
+ }
+ LoadStoreActions.clampScalar(0, s32, sXLen).lower();
ExtLoadActions.widenScalarToNextPow2(0).clampScalar(0, s32, sXLen).lower();
getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, sXLen}});
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