[llvm] [RISCV][GISel] Add really basic support for FP regbank selection for G_LOAD/G_STORE. (PR #70896)
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llvm-commits at lists.llvm.org
Tue Oct 31 22:39:51 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
Coerce the register bank based on the users of the G_LOAD or the defining instruction for the G_STORE.
No tests for RV32 because we need to make s64 load/store legal for rv32 with D extension first.
---
Full diff: https://github.com/llvm/llvm-project/pull/70896.diff
3 Files Affected:
- (modified) llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp (+1)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp (+80-2)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-use-def.mir (+105)
``````````diff
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b956cd4782b7943..7baafe2b177663c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -868,6 +868,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// Check if that store is fed by fp instructions.
if (OpRegBankIdx[0] == PMI_FirstGPR) {
Register VReg = MI.getOperand(0).getReg();
+ assert(VReg);
if (!VReg)
break;
MachineInstr *DefMI = MRI.getVRegDef(VReg);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index f005948d2094445..aa59dff5266b3ea 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -103,6 +103,51 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
}
}
+// TODO: Make this more like AArch64?
+static bool onlyUsesFP(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_FADD:
+ case TargetOpcode::G_FSUB:
+ case TargetOpcode::G_FMUL:
+ case TargetOpcode::G_FDIV:
+ case TargetOpcode::G_FNEG:
+ case TargetOpcode::G_FABS:
+ case TargetOpcode::G_FSQRT:
+ case TargetOpcode::G_FMAXNUM:
+ case TargetOpcode::G_FMINNUM:
+ case TargetOpcode::G_FPEXT:
+ case TargetOpcode::G_FPTRUNC:
+ case TargetOpcode::G_FCMP:
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
+// TODO: Make this more like AArch64?
+static bool onlyDefinesFP(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_FADD:
+ case TargetOpcode::G_FSUB:
+ case TargetOpcode::G_FMUL:
+ case TargetOpcode::G_FDIV:
+ case TargetOpcode::G_FNEG:
+ case TargetOpcode::G_FABS:
+ case TargetOpcode::G_FSQRT:
+ case TargetOpcode::G_FMAXNUM:
+ case TargetOpcode::G_FMINNUM:
+ case TargetOpcode::G_FPEXT:
+ case TargetOpcode::G_FPTRUNC:
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
const RegisterBankInfo::InstructionMapping &
RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
const unsigned Opc = MI.getOpcode();
@@ -149,11 +194,44 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
- case TargetOpcode::G_LOAD:
case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD:
- case TargetOpcode::G_STORE:
break;
+ case TargetOpcode::G_LOAD:
+ // Check if that load feeds fp instructions.
+ // In that case, we want the default mapping to be on FPR
+ // instead of blind map every scalar to GPR.
+ if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
+ [&](const MachineInstr &UseMI) {
+ // If we have at least one direct use in a FP instruction,
+ // assume this was a floating point load in the IR. If it was
+ // not, we would have had a bitcast before reaching that
+ // instruction.
+ return onlyUsesFP(UseMI);
+ })) {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ if (Ty.getSizeInBits() == 64)
+ OperandsMapping = getOperandsMapping(
+ {&RISCV::ValueMappings[RISCV::FPR64Idx], GPRValueMapping});
+ else
+ OperandsMapping = getOperandsMapping(
+ {&RISCV::ValueMappings[RISCV::FPR32Idx], GPRValueMapping});
+ }
+
+ break;
+ case TargetOpcode::G_STORE: {
+ MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
+ if (onlyDefinesFP(*DefMI)) {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ if (Ty.getSizeInBits() == 64)
+ OperandsMapping = getOperandsMapping(
+ {&RISCV::ValueMappings[RISCV::FPR64Idx], GPRValueMapping});
+ else
+ OperandsMapping = getOperandsMapping(
+ {&RISCV::ValueMappings[RISCV::FPR32Idx], GPRValueMapping});
+ }
+ break;
+ }
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-use-def.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-use-def.mir
new file mode 100644
index 000000000000000..a741d3345be19d3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-use-def.mir
@@ -0,0 +1,105 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fp_store_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10, $f10_f, $f11_f
+
+ ; CHECK-LABEL: name: fp_store_f32
+ ; CHECK: liveins: $x10, $f10_f, $f11_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: G_STORE [[FADD]](s32), [[COPY]](p0) :: (store (s32))
+ ; CHECK-NEXT: PseudoRET
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = COPY $f10_f
+ %2:_(s32) = COPY $f11_f
+ %3:_(s32) = G_FADD %1, %2
+ G_STORE %3(s32), %0(p0) :: (store (s32))
+ PseudoRET
+
+...
+---
+name: fp_store_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10, $f10_d, $f11_d
+
+ ; CHECK-LABEL: name: fp_store_f64
+ ; CHECK: liveins: $x10, $f10_d, $f11_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $f11_d
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: G_STORE [[FADD]](s64), [[COPY]](p0) :: (store (s64))
+ ; CHECK-NEXT: PseudoRET
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = COPY $f10_d
+ %2:_(s64) = COPY $f11_d
+ %3:_(s64) = G_FADD %1, %2
+ G_STORE %3(s64), %0(p0) :: (store (s64))
+ PseudoRET
+
+...
+---
+name: fp_load_f32
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10, $f10_f
+
+ ; CHECK-LABEL: name: fp_load_f32
+ ; CHECK: liveins: $x10, $f10_f
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-NEXT: $f10_f = COPY [[FADD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $f10_f
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = COPY $f10_f
+ %2:_(s32) = G_LOAD %0(p0) :: (load (s32))
+ %3:_(s32) = G_FADD %2, %1
+ $f10_f = COPY %3(s32)
+ PseudoRET implicit $f10_f
+
+...
+---
+name: fp_load_f64
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10, $f10_d
+
+ ; CHECK-LABEL: name: fp_load_f64
+ ; CHECK: liveins: $x10, $f10_d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f10_d
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[LOAD]], [[COPY1]]
+ ; CHECK-NEXT: $f10_d = COPY [[FADD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $f10_d
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = COPY $f10_d
+ %2:_(s64) = G_LOAD %0(p0) :: (load (s64))
+ %3:_(s64) = G_FADD %2, %1
+ $f10_d = COPY %3(s64)
+ PseudoRET implicit $f10_d
+
+...
``````````
</details>
https://github.com/llvm/llvm-project/pull/70896
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