[llvm] [AArch64][GlobalISel] Support udot lowering for vecreduce add (PR #70784)

[Amara Emerson via llvm-commits]

https://github.com/aemerson commented:

I didn't realize the predicates would work in the combiner tablegen files. Can you add a RUN line for GISel without +dotprod to check it doesn't produce udot in those cases? I suggest you precommit that test change and then rebase this patch on top of it.

https://github.com/llvm/llvm-project/pull/70784