[llvm] 0e8cbb6 - [SLP][NFC]Add a test with poisonous reduction, seeding bool logical op.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2023-10-31T12:10:10-07:00
New Revision: 0e8cbb6ac8dc56104f200ce6f92008a315ccc267

URL: https://github.com/llvm/llvm-project/commit/0e8cbb6ac8dc56104f200ce6f92008a315ccc267
DIFF: https://github.com/llvm/llvm-project/commit/0e8cbb6ac8dc56104f200ce6f92008a315ccc267.diff

LOG: [SLP][NFC]Add a test with poisonous reduction, seeding bool logical op.
NFC.

Added: 
    

Modified: 
    llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
index b66967d183cacce..1070c49093821ef 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction-bool-logic-op-inside.ll
@@ -17,3 +17,28 @@ define i1 @test(i32 %x) {
   ret i1 %ret
 }
 
+define i1 @test1(i32 %x, i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK-LABEL: define i1 @test1(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[D]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[A]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[B]], i32 3
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp sgt <4 x i32> [[TMP4]], <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[C]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
+; CHECK-NEXT:    [[OP_RDX:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP3]]
+; CHECK-NEXT:    ret i1 [[OP_RDX]]
+;
+  %cmp = icmp sgt i32 %x, 1
+  %cmp1 = icmp sgt i32 %a, 1
+  %cmp2 = icmp sgt i32 %b, 1
+  %cmp3 = icmp sgt i32 %c, 1
+  %cmp4 = icmp sgt i32 %d, 1
+  %sel1 = select i1 %cmp, i1 true, i1 %cmp1
+  %sel2 = select i1 %sel1, i1 true, i1 %cmp2
+  %sel3 = select i1 %sel2, i1 true, i1 %cmp3
+  %sel4 = select i1 %cmp, i1 true, i1 %cmp4
+  %ret = or i1 %sel3, %sel4
+  ret i1 %ret
+}