[llvm] [RISCV] RISC-V split register allocation and move vsetvl pass in between (PR #70549)

[Michael Maitland via llvm-commits]

================
@@ -83,6 +84,10 @@ static cl::opt<bool>
                    cl::desc("Enable sinking and folding of instruction copies"),
                    cl::init(false), cl::Hidden);
 
+static cl::opt<bool> EnableSplitRA("riscv-split-RA", cl::Hidden,
+                                   cl::desc("Enable Split RA for RVV"),
----------------
michaelmaitland wrote:

A user may not know what `RA` is. I suggest changing it to `riscv-split-regalloc`, `EnableSplitRegAlloc`, and `Enable Split RegisterAlloc for RVV`.

https://github.com/llvm/llvm-project/pull/70549