[llvm] [WIP] - [LLVM][SVE] Honour NEON calling convention when targeting SVE VLS. (PR #70847)

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git-clang-format --diff f87af714a555ad06c9d212ae3c333294d366b76d 681cb3550d5463e1a1853bcab3a0edc0fcc0f435 -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b64e05600592..bada47d37093 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26544,22 +26544,21 @@ bool AArch64TargetLowering::preferScalarizeSplat(SDNode *N) const {
 }
 
 MVT AArch64TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
-                                                      CallingConv::ID CC,
-                                                      EVT VT) const {
+                                                         CallingConv::ID CC,
+                                                         EVT VT) const {
   if (!VT.isFixedLengthVector() || VT.getFixedSizeInBits() <= 128)
     return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 
   EVT VT1;
   MVT RegisterVT;
   unsigned NumIntermediates;
-  getVectorTypeBreakdownForCallingConv(Context, CC, VT, VT1,
-                                       NumIntermediates, RegisterVT);
+  getVectorTypeBreakdownForCallingConv(Context, CC, VT, VT1, NumIntermediates,
+                                       RegisterVT);
   return RegisterVT;
 }
 
-unsigned AArch64TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
-                                                           CallingConv::ID CC,
-                                                           EVT VT) const {
+unsigned AArch64TargetLowering::getNumRegistersForCallingConv(
+    LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
   if (!VT.isFixedLengthVector() || VT.getFixedSizeInBits() <= 128)
     return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
 
@@ -26570,8 +26569,11 @@ unsigned AArch64TargetLowering::getNumRegistersForCallingConv(LLVMContext &Conte
                                               NumIntermediates, VT2);
 }
 
-unsigned AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const {
-  int NumRegs = TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
+unsigned AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(
+    LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
+    unsigned &NumIntermediates, MVT &RegisterVT) const {
+  int NumRegs = TargetLowering::getVectorTypeBreakdownForCallingConv(
+      Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
   if (!RegisterVT.isFixedLengthVector() ||
       RegisterVT.getFixedSizeInBits() <= 128)
     return NumRegs;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 2e53481c03e1..244c72efed4c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -952,9 +952,11 @@ public:
   unsigned getNumRegistersForCallingConv(LLVMContext &Context,
                                          CallingConv::ID CC,
                                          EVT VT) const override;
-  unsigned getVectorTypeBreakdownForCallingConv(
-      LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
-      unsigned &NumIntermediates, MVT &RegisterVT) const override;
+  unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
+                                                CallingConv::ID CC, EVT VT,
+                                                EVT &IntermediateVT,
+                                                unsigned &NumIntermediates,
+                                                MVT &RegisterVT) const override;
 
 private:
   /// Keep a pointer to the AArch64Subtarget around so that we can

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https://github.com/llvm/llvm-project/pull/70847