[llvm] [RISCV][GISel] Simplify selectSelect. NFC (PR #70846)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/70846

>From 9069bf98d62c5cc158ed3c2a515d182d55572850 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 31 Oct 2023 11:05:17 -0700
Subject: [PATCH 1/2] [RISCV][GISel] Simplify selectSelect. NFC

Use GSelect and reduce number of temporaries.
---
 .../RISCV/GISel/RISCVInstructionSelector.cpp  | 28 +++++++++----------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index b03be71ed7b2a6f..908fb74b8e406c1 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -776,27 +776,25 @@ static void getICMPOperandsForBranch(MachineInstr &MI, MachineIRBuilder &MIB,
 bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
                                             MachineIRBuilder &MIB,
                                             MachineRegisterInfo &MRI) const {
-  assert(MI.getOpcode() == TargetOpcode::G_SELECT);
+  auto &SelectMI = cast<GSelect>(MI);
 
   // If MI is a G_SELECT(G_ICMP(tst, A, B), C, D) then we can use (A, B, tst)
   // as the (LHS, RHS, CC) of the Select_GPR_Using_CC_GPR.
-  Register MIOp1Reg = MI.getOperand(1).getReg();
-  bool Op1IsICMP = mi_match(MIOp1Reg, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()));
-  RISCVCC::CondCode CC;
-  Register LHS, RHS;
+  Register LHS = SelectMI.getCondReg();
+  Register RHS = RISCV::X0;
+  RISCVCC::CondCode CC = RISCVCC::COND_NE;
+
+  bool Op1IsICMP = mi_match(LHS, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()));
   if (Op1IsICMP)
-    getICMPOperandsForBranch(*MRI.getVRegDef(MIOp1Reg), MIB, MRI, CC, LHS, RHS);
+    getICMPOperandsForBranch(*MRI.getVRegDef(LHS), MIB, MRI, CC, LHS, RHS);
 
-  Register Op1 = Op1IsICMP ? LHS : MI.getOperand(1).getReg();
-  Register Op2 = Op1IsICMP ? RHS : RISCV::X0;
-  unsigned Op3 = Op1IsICMP ? CC : RISCVCC::COND_NE;
   MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
-                             .addDef(MI.getOperand(0).getReg())
-                             .addReg(Op1)
-                             .addReg(Op2)
-                             .addImm(Op3)
-                             .addReg(MI.getOperand(2).getReg())
-                             .addReg(MI.getOperand(3).getReg());
+                             .addDef(SelectMI.getReg(0))
+                             .addReg(LHS)
+                             .addReg(RHS)
+                             .addImm(CC)
+                             .addReg(SelectMI.getTrueReg())
+                             .addReg(SelectMI.getFalseReg());
   MI.eraseFromParent();
   return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI);
 }

>From fbbd4c20f85e81fdb8c2c0d3e1a5c0c2de22c923 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 31 Oct 2023 11:19:16 -0700
Subject: [PATCH 2/2] Fold mi_match into if

---
 llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 908fb74b8e406c1..698168f6a8012e9 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -784,8 +784,7 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
   Register RHS = RISCV::X0;
   RISCVCC::CondCode CC = RISCVCC::COND_NE;
 
-  bool Op1IsICMP = mi_match(LHS, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()));
-  if (Op1IsICMP)
+  if (mi_match(LHS, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg())))
     getICMPOperandsForBranch(*MRI.getVRegDef(LHS), MIB, MRI, CC, LHS, RHS);
 
   MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)