[llvm] [AArch64][GlobalISel] TableGen Selection for G_VECREDUCE_ADD (PR #70785)

[Vladislav Dzhidzhoev via llvm-commits]

================
@@ -6637,6 +6637,21 @@ def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
           ssub))>;
 }
 
+def : Pat<(i8 (vecreduce_add (v8i8 V64:$Rn))), 
----------------
dzhidzhoev wrote:

Shouldn't this be located in llvm/lib/Target/AArch64/AArch64InstrGISel.td?

https://github.com/llvm/llvm-project/pull/70785