[llvm] [AMDGPU] Folding imm offset in more cases for scratch access (PR #70634)

[via llvm-commits]

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@@ -1146,10 +1146,23 @@ bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0,
   return CurDAG->SignBitIsZero(Base);
 }
 
-bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegal(SDValue Base,
+bool AMDGPUDAGToDAGISel::isFlatScratchBaseLegal(SDValue Addr, SDValue Base,
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ruiling wrote:

I think the whole address will be passed to the `Addr` instead of base in the case `saddr+ioffset` and `vaddr+ioffset`? see `AMDGPUDAGToDAGISel::SelectFlatOffsetImpl()` and `AMDGPUDAGToDAGISel::SelectScratchSAddr()`. I am trying to add some comment locally explaining the function:
```
// This is used to check whether the address of scratch_load/store in the
// form of `base + immediate offset` is legal with respect to the hardware's
// requirement that the SGPR/VGPR address offset in the flat scratch instruction
// should be unsigned.
```

https://github.com/llvm/llvm-project/pull/70634