[llvm] [PowerPC] Change triple of test due to AIX ABI breakage. NFC. (PR #70758)

[Kai Luo via llvm-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/70758

>From fb7405fe70450947afcbe43b09b4e23bb43f14df Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Tue, 31 Oct 2023 02:14:31 +0000
Subject: [PATCH 1/3] [PowerPC] Change the triple of the test due to ABI
 breakage. NFC.

---
 llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
index f82d794a1ede81d..7efe0953f630fdc 100644
--- a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
+++ b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
@@ -1,4 +1,4 @@
-# RUN: llc -simplify-mir -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+# RUN: llc -simplify-mir -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 # RUN:   %s -o - | FileCheck %s
 
 ---

>From c71c9a802be58e287372ca6712f9f0ec7ed8eec2 Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Tue, 31 Oct 2023 02:22:41 +0000
Subject: [PATCH 2/3] Up

---
 .../CodeGen/PowerPC/ldst-16-byte-asm-aix.mir  | 23 +++++++++++++++++++
 .../test/CodeGen/PowerPC/ldst-16-byte-asm.mir |  2 +-
 2 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/PowerPC/ldst-16-byte-asm-aix.mir

diff --git a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm-aix.mir b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm-aix.mir
new file mode 100644
index 000000000000000..1807f1b8da9f38e
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm-aix.mir
@@ -0,0 +1,23 @@
+# RUN: llc -simplify-mir -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+# RUN:   %s -o - | FileCheck %s
+
+---
+name: foo
+alignment: 8
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+  liveins: $x3, $x4, $x5, $x6
+    ; CHECK-LABEL: .foo
+    ; CHECK: lq 2, 128(4)
+    ; CHECK: lqarx 28, 5, 6
+    ; CHECK: stqcx. 28, 5, 6
+    ; CHECK: stq 2, 128(4)
+  $g8p1 = LQ 128, $x4
+  $g8p14 = LQARX $x5, $x6
+  STQCX $g8p14, $x5, $x6, implicit-def $cr0
+  STQ $g8p1, 128, $x4
+  $x3 = COPY $x6
+  BLR8 implicit $lr8, implicit undef $rm, implicit $x3
+...
+
diff --git a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
index 7efe0953f630fdc..c66ad1eadc702da 100644
--- a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
+++ b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
@@ -8,7 +8,7 @@ tracksRegLiveness: true
 body: |
   bb.0.entry:
   liveins: $x3, $x4, $x30, $x31
-    ; CHECK-LABEL: .foo
+    ; CHECK-LABEL: foo
     ; CHECK: lq 2, 128(4)
     ; CHECK: lqarx 28, 30, 31
     ; CHECK: stqcx. 28, 30, 31

>From 751ee5d03dfbce6ece3473a1c4bed9f9d1356497 Mon Sep 17 00:00:00 2001
From: Kai Luo <lkail at cn.ibm.com>
Date: Tue, 31 Oct 2023 02:49:24 +0000
Subject: [PATCH 3/3] Do not use CSR

---
 llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
index c66ad1eadc702da..b9f3906a315b0f0 100644
--- a/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
+++ b/llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
@@ -7,17 +7,17 @@ alignment: 8
 tracksRegLiveness: true
 body: |
   bb.0.entry:
-  liveins: $x3, $x4, $x30, $x31
+  liveins: $x3, $x4, $x5, $x6
     ; CHECK-LABEL: foo
     ; CHECK: lq 2, 128(4)
     ; CHECK: lqarx 28, 30, 31
     ; CHECK: stqcx. 28, 30, 31
     ; CHECK: stq 2, 128(4)
   $g8p1 = LQ 128, $x4
-  $g8p14 = LQARX $x30, $x31
-  STQCX $g8p14, $x30, $x31, implicit-def $cr0
+  $g8p14 = LQARX $x5, $x6
+  STQCX $g8p14, $x5, $x6, implicit-def $cr0
   STQ $g8p1, 128, $x4
-  $x3 = COPY $x31
+  $x3 = COPY $x6
   BLR8 implicit $lr8, implicit undef $rm, implicit $x3
 ...