[lld] [lld] Add support for EC code map. (PR #69101)
Jacek Caban via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 30 13:41:27 PDT 2023
https://github.com/cjacek updated https://github.com/llvm/llvm-project/pull/69101
>From 7cf2da25f79b7073b705e3a39b849d2d6329f829 Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek at codeweavers.com>
Date: Mon, 30 Oct 2023 14:19:17 +0100
Subject: [PATCH 1/4] [lld] Implement getOutputCharacteristics for non-section
code thunks.
This will be useful for ARM64EC, but it also fixes MinGW export handling when synthetic function symbols are exported.
---
lld/COFF/Chunks.h | 18 ++++++++++++++----
lld/COFF/DLL.cpp | 16 ++++++++--------
lld/test/COFF/export-thunk.test | 14 ++++++++++++++
3 files changed, 36 insertions(+), 12 deletions(-)
create mode 100644 lld/test/COFF/export-thunk.test
diff --git a/lld/COFF/Chunks.h b/lld/COFF/Chunks.h
index cbfeb5c025adbb2..b82bc9416775d7c 100644
--- a/lld/COFF/Chunks.h
+++ b/lld/COFF/Chunks.h
@@ -180,6 +180,16 @@ class NonSectionChunk : public Chunk {
NonSectionChunk(Kind k = OtherKind) : Chunk(k) {}
};
+class NonSectionCodeChunk : public NonSectionChunk {
+public:
+ virtual uint32_t getOutputCharacteristics() const override {
+ return llvm::COFF::IMAGE_SCN_MEM_READ | llvm::COFF::IMAGE_SCN_MEM_EXECUTE;
+ }
+
+protected:
+ NonSectionCodeChunk(Kind k = OtherKind) : NonSectionChunk(k) {}
+};
+
// MinGW specific; information about one individual location in the image
// that needs to be fixed up at runtime after loading. This represents
// one individual element in the PseudoRelocTableChunk table.
@@ -508,10 +518,10 @@ static const uint8_t importThunkARM64[] = {
// Windows-specific.
// A chunk for DLL import jump table entry. In a final output, its
// contents will be a JMP instruction to some __imp_ symbol.
-class ImportThunkChunk : public NonSectionChunk {
+class ImportThunkChunk : public NonSectionCodeChunk {
public:
ImportThunkChunk(COFFLinkerContext &ctx, Defined *s)
- : NonSectionChunk(ImportThunkKind), impSymbol(s), ctx(ctx) {}
+ : NonSectionCodeChunk(ImportThunkKind), impSymbol(s), ctx(ctx) {}
static bool classof(const Chunk *c) { return c->kind() == ImportThunkKind; }
protected:
@@ -560,7 +570,7 @@ class ImportThunkChunkARM64 : public ImportThunkChunk {
MachineTypes getMachine() const override { return ARM64; }
};
-class RangeExtensionThunkARM : public NonSectionChunk {
+class RangeExtensionThunkARM : public NonSectionCodeChunk {
public:
explicit RangeExtensionThunkARM(COFFLinkerContext &ctx, Defined *t)
: target(t), ctx(ctx) {
@@ -576,7 +586,7 @@ class RangeExtensionThunkARM : public NonSectionChunk {
COFFLinkerContext &ctx;
};
-class RangeExtensionThunkARM64 : public NonSectionChunk {
+class RangeExtensionThunkARM64 : public NonSectionCodeChunk {
public:
explicit RangeExtensionThunkARM64(COFFLinkerContext &ctx, Defined *t)
: target(t), ctx(ctx) {
diff --git a/lld/COFF/DLL.cpp b/lld/COFF/DLL.cpp
index 0b337a209c377db..6b516d8c6d5ef89 100644
--- a/lld/COFF/DLL.cpp
+++ b/lld/COFF/DLL.cpp
@@ -313,7 +313,7 @@ static const uint8_t tailMergeARM64[] = {
};
// A chunk for the delay import thunk.
-class ThunkChunkX64 : public NonSectionChunk {
+class ThunkChunkX64 : public NonSectionCodeChunk {
public:
ThunkChunkX64(Defined *i, Chunk *tm) : imp(i), tailMerge(tm) {}
@@ -330,7 +330,7 @@ class ThunkChunkX64 : public NonSectionChunk {
Chunk *tailMerge = nullptr;
};
-class TailMergeChunkX64 : public NonSectionChunk {
+class TailMergeChunkX64 : public NonSectionCodeChunk {
public:
TailMergeChunkX64(Chunk *d, Defined *h) : desc(d), helper(h) {}
@@ -382,7 +382,7 @@ class TailMergeUnwindInfoX64 : public NonSectionChunk {
}
};
-class ThunkChunkX86 : public NonSectionChunk {
+class ThunkChunkX86 : public NonSectionCodeChunk {
public:
ThunkChunkX86(COFFLinkerContext &ctx, Defined *i, Chunk *tm)
: imp(i), tailMerge(tm), ctx(ctx) {}
@@ -407,7 +407,7 @@ class ThunkChunkX86 : public NonSectionChunk {
const COFFLinkerContext &ctx;
};
-class TailMergeChunkX86 : public NonSectionChunk {
+class TailMergeChunkX86 : public NonSectionCodeChunk {
public:
TailMergeChunkX86(COFFLinkerContext &ctx, Chunk *d, Defined *h)
: desc(d), helper(h), ctx(ctx) {}
@@ -432,7 +432,7 @@ class TailMergeChunkX86 : public NonSectionChunk {
const COFFLinkerContext &ctx;
};
-class ThunkChunkARM : public NonSectionChunk {
+class ThunkChunkARM : public NonSectionCodeChunk {
public:
ThunkChunkARM(COFFLinkerContext &ctx, Defined *i, Chunk *tm)
: imp(i), tailMerge(tm), ctx(ctx) {
@@ -459,7 +459,7 @@ class ThunkChunkARM : public NonSectionChunk {
const COFFLinkerContext &ctx;
};
-class TailMergeChunkARM : public NonSectionChunk {
+class TailMergeChunkARM : public NonSectionCodeChunk {
public:
TailMergeChunkARM(COFFLinkerContext &ctx, Chunk *d, Defined *h)
: desc(d), helper(h), ctx(ctx) {
@@ -486,7 +486,7 @@ class TailMergeChunkARM : public NonSectionChunk {
const COFFLinkerContext &ctx;
};
-class ThunkChunkARM64 : public NonSectionChunk {
+class ThunkChunkARM64 : public NonSectionCodeChunk {
public:
ThunkChunkARM64(Defined *i, Chunk *tm) : imp(i), tailMerge(tm) {
setAlignment(4);
@@ -506,7 +506,7 @@ class ThunkChunkARM64 : public NonSectionChunk {
Chunk *tailMerge = nullptr;
};
-class TailMergeChunkARM64 : public NonSectionChunk {
+class TailMergeChunkARM64 : public NonSectionCodeChunk {
public:
TailMergeChunkARM64(Chunk *d, Defined *h) : desc(d), helper(h) {
setAlignment(4);
diff --git a/lld/test/COFF/export-thunk.test b/lld/test/COFF/export-thunk.test
new file mode 100644
index 000000000000000..85e0e92bc0639b7
--- /dev/null
+++ b/lld/test/COFF/export-thunk.test
@@ -0,0 +1,14 @@
+REQUIRES: x86
+
+RUN: echo -e 'LIBRARY test.dll\nEXPORTS\nimpfunc\n' > %t.imp.def
+RUN: llvm-dlltool -m i386:x86-64 -d %t.imp.def -l %t.imp.lib
+RUN: lld-link -machine:amd64 -out:%t.dll -dll -noentry -lldmingw %t.imp.lib -export:impfunc -output-def:%t.def
+
+Check that the synthetic import thunk is exported as a function, not data.
+
+RUN: cat %t.def | FileCheck %s
+CHECK: EXPORTS
+CHECK-NEXT: impfunc @1
+
+RUN: cat %t.def | FileCheck -check-prefix=CHECK-NO-DATA %s
+CHECK-NO-DATA-NOT: DATA
>From cb3d1cc1df7f476f4b7eb3da118ed1038d115e24 Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek at codeweavers.com>
Date: Mon, 30 Oct 2023 20:47:43 +0100
Subject: [PATCH 2/4] [lld] Sort data chunks before code chunks on ARM64EC.
---
lld/COFF/Chunks.h | 8 +++++--
lld/COFF/Writer.cpp | 4 +++-
lld/test/COFF/arm64ec-codemap.test | 38 ++++++++++++++++++++++++++++++
3 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/lld/COFF/Chunks.h b/lld/COFF/Chunks.h
index b82bc9416775d7c..156e7a807cb8fd7 100644
--- a/lld/COFF/Chunks.h
+++ b/lld/COFF/Chunks.h
@@ -116,7 +116,7 @@ class Chunk {
bool isHotPatchable() const;
MachineTypes getMachine() const;
- chpe_range_type getArm64ECRangeType() const;
+ std::optional<chpe_range_type> getArm64ECRangeType() const;
protected:
Chunk(Kind k = OtherKind) : chunkKind(k), hasData(true), p2Align(0) {}
@@ -437,7 +437,11 @@ inline MachineTypes Chunk::getMachine() const {
return static_cast<const NonSectionChunk *>(this)->getMachine();
}
-inline chpe_range_type Chunk::getArm64ECRangeType() const {
+inline std::optional<chpe_range_type> Chunk::getArm64ECRangeType() const {
+ // Data sections don't need codemap entries.
+ if (!(getOutputCharacteristics() & llvm::COFF::IMAGE_SCN_MEM_EXECUTE))
+ return std::nullopt;
+
switch (getMachine()) {
case AMD64:
return chpe_range_type::Amd64;
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index 43d8e7c1d530859..895a6e00710c634 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -1389,7 +1389,9 @@ void Writer::sortECChunks() {
for (OutputSection *sec : ctx.outputSections) {
if (sec->isCodeSection())
llvm::stable_sort(sec->chunks, [=](const Chunk *a, const Chunk *b) {
- return a->getArm64ECRangeType() < b->getArm64ECRangeType();
+ std::optional<chpe_range_type> aType = a->getArm64ECRangeType(),
+ bType = b->getArm64ECRangeType();
+ return !aType || (bType && *aType < *bType);
});
}
}
diff --git a/lld/test/COFF/arm64ec-codemap.test b/lld/test/COFF/arm64ec-codemap.test
index 424456a6dee66f0..018810a86a34f22 100644
--- a/lld/test/COFF/arm64ec-codemap.test
+++ b/lld/test/COFF/arm64ec-codemap.test
@@ -110,6 +110,40 @@ DISASMM-NEXT: ...
DISASMM-NEXT: 180002ffe: 00 00 addb %al, (%rax)
DISASMM-NEXT: 180003000: b8 06 00 00 00 movl $0x6, %eax
+RUN: lld-link -out:testdm.dll -machine:arm64ec arm64ec-func-sym.obj x86_64-func-sym.obj codemap.obj \
+RUN: data-sec.obj loadconfig-arm64ec.obj -dll -noentry -merge:.testdata=.text -merge:.rdata=test
+
+RUN: llvm-readobj --coff-load-config testdm.dll | FileCheck -check-prefix=CODEMAPDM %s
+CODEMAPDM: CodeMap [
+CODEMAPDM-NEXT: 0x2000 - 0x2008 ARM64EC
+CODEMAPDM-NEXT: 0x3000 - 0x3006 X64
+CODEMAPDM-NEXT: 0x5200 - 0x5208 ARM64EC
+CODEMAPDM-NEXT: 0x6000 - 0x6006 X64
+CODEMAPDM-NEXT: ]
+
+Merging code data into code sections causes data to be separated from the code when sorting chunks.
+
+RUN: llvm-objdump -d testdm.dll | FileCheck -check-prefix=DISASMDM %s
+DISASMDM: Disassembly of section .text:
+DISASMDM-EMPTY:
+DISASMDM-NEXT: 0000000180001000 <.text>:
+DISASMDM-NEXT: 180001000: 00000001 udf #0x1
+DISASMDM-NEXT: ...
+DISASMDM-NEXT: 180002000: 52800040 mov w0, #0x2
+DISASMDM-NEXT: 180002004: d65f03c0 ret
+DISASMDM-NEXT: ...
+DISASMDM-NEXT: 180003000: b8 03 00 00 00 movl $0x3, %eax
+DISASMDM-NEXT: 180003005: c3 retq
+DISASMDM-EMPTY:
+DISASMDM-NEXT: Disassembly of section test:
+DISASMDM-EMPTY:
+DISASMDM-NEXT: 0000000180005000 <test>:
+DISASMDM: 180005200: 528000a0 mov w0, #0x5
+DISASMDM-NEXT: 180005204: d65f03c0 ret
+DISASMDM-NEXT: ...
+DISASMDM-NEXT: 180006000: b8 06 00 00 00 movl $0x6, %eax
+DISASMDM-NEXT: 180006005: c3 retq
+
#--- arm64-func-sym.s
.text
.globl arm64_func_sym
@@ -148,6 +182,10 @@ x86_64_func_sym2:
movl $6, %eax
retq
+#--- data-sec.s
+ .section .testdata, "rd"
+ .xword 1
+
#--- codemap.s
.section .rdata,"dr"
.globl code_map
>From 6314e783287b5930045933d1a28f0c370a84b10b Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek at codeweavers.com>
Date: Fri, 5 May 2023 00:41:47 +0200
Subject: [PATCH 3/4] [lld] Align EC code region boundaries.
Boundaries between code chunks of different architecture are always aligned. 0x1000 seems to be a constant, this does not seem to be affected by any command line alignment argument.
---
lld/COFF/Writer.cpp | 9 +++++++++
lld/test/COFF/arm64ec-codemap.test | 28 ++++++++++++++--------------
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index 895a6e00710c634..960328d686852a3 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -1423,8 +1423,17 @@ void Writer::assignAddresses() {
// If /FUNCTIONPADMIN is used, functions are padded in order to create a
// hotpatchable image.
uint32_t padding = sec->isCodeSection() ? config->functionPadMin : 0;
+ std::optional<chpe_range_type> prevECRange;
for (Chunk *c : sec->chunks) {
+ // Alignment EC code range baudaries.
+ if (isArm64EC(ctx.config.machine) && sec->isCodeSection()) {
+ std::optional<chpe_range_type> rangeType = c->getArm64ECRangeType();
+ if (rangeType != prevECRange) {
+ virtualSize = alignTo(virtualSize, 4096);
+ prevECRange = rangeType;
+ }
+ }
if (padding && c->isHotPatchable())
virtualSize += padding;
virtualSize = alignTo(virtualSize, c->getAlignment());
diff --git a/lld/test/COFF/arm64ec-codemap.test b/lld/test/COFF/arm64ec-codemap.test
index 018810a86a34f22..131644c4983ca3d 100644
--- a/lld/test/COFF/arm64ec-codemap.test
+++ b/lld/test/COFF/arm64ec-codemap.test
@@ -92,7 +92,7 @@ RUN: codemap3.obj loadconfig-arm64ec.obj -dll -noentry -merge:test=.tex
RUN: llvm-readobj --coff-load-config testm.dll | FileCheck -check-prefix=CODEMAPM %s
CODEMAPM: CodeMap [
CODEMAPM-NEXT: 0x1000 - 0x1010 ARM64EC
-CODEMAPM-NEXT: 0x2000 - 0x3004 X64
+CODEMAPM-NEXT: 0x2000 - 0x200E X64
CODEMAPM-NEXT: ]
RUN: llvm-objdump -d testm.dll | FileCheck -check-prefix=DISASMM %s
@@ -106,9 +106,9 @@ DISASMM-NEXT: 18000100c: d65f03c0 ret
DISASMM-NEXT: ...
DISASMM-NEXT: 180002000: b8 03 00 00 00 movl $0x3, %eax
DISASMM-NEXT: 180002005: c3 retq
-DISASMM-NEXT: ...
-DISASMM-NEXT: 180002ffe: 00 00 addb %al, (%rax)
-DISASMM-NEXT: 180003000: b8 06 00 00 00 movl $0x6, %eax
+DISASMM-NEXT: 180002006: 00 00 addb %al, (%rax)
+DISASMM-NEXT: 180002008: b8 06 00 00 00 movl $0x6, %eax
+DISASMM-NEXT: 18000200d: c3 retq
RUN: lld-link -out:testdm.dll -machine:arm64ec arm64ec-func-sym.obj x86_64-func-sym.obj codemap.obj \
RUN: data-sec.obj loadconfig-arm64ec.obj -dll -noentry -merge:.testdata=.text -merge:.rdata=test
@@ -117,8 +117,8 @@ RUN: llvm-readobj --coff-load-config testdm.dll | FileCheck -check-prefix=CODEMA
CODEMAPDM: CodeMap [
CODEMAPDM-NEXT: 0x2000 - 0x2008 ARM64EC
CODEMAPDM-NEXT: 0x3000 - 0x3006 X64
-CODEMAPDM-NEXT: 0x5200 - 0x5208 ARM64EC
-CODEMAPDM-NEXT: 0x6000 - 0x6006 X64
+CODEMAPDM-NEXT: 0x6000 - 0x6008 ARM64EC
+CODEMAPDM-NEXT: 0x7000 - 0x7006 X64
CODEMAPDM-NEXT: ]
Merging code data into code sections causes data to be separated from the code when sorting chunks.
@@ -138,11 +138,11 @@ DISASMDM-EMPTY:
DISASMDM-NEXT: Disassembly of section test:
DISASMDM-EMPTY:
DISASMDM-NEXT: 0000000180005000 <test>:
-DISASMDM: 180005200: 528000a0 mov w0, #0x5
-DISASMDM-NEXT: 180005204: d65f03c0 ret
+DISASMDM: 180006000: 528000a0 mov w0, #0x5
+DISASMDM-NEXT: 180006004: d65f03c0 ret
DISASMDM-NEXT: ...
-DISASMDM-NEXT: 180006000: b8 06 00 00 00 movl $0x6, %eax
-DISASMDM-NEXT: 180006005: c3 retq
+DISASMDM-NEXT: 180007000: b8 06 00 00 00 movl $0x6, %eax
+DISASMDM-NEXT: 180007005: c3 retq
#--- arm64-func-sym.s
.text
@@ -155,7 +155,7 @@ arm64_func_sym:
#--- arm64ec-func-sym.s
.text
.globl arm64ec_func_sym
- .p2align 12, 0x0
+ .p2align 2, 0x0
arm64ec_func_sym:
mov w0, #2
ret
@@ -170,14 +170,14 @@ arm64ec_func_sym2:
#--- x86_64-func-sym.s
.text
.globl x86_64_func_sym
- .p2align 12, 0x0
+ .p2align 2, 0x0
x86_64_func_sym:
movl $3, %eax
retq
.section test, "xr"
.globl x86_64_func_sym2
- .p2align 12, 0x0
+ .p2align 2, 0x0
x86_64_func_sym2:
movl $6, %eax
retq
@@ -227,7 +227,7 @@ code_map:
.rva arm64ec_func_sym + 1
.word 16
.rva x86_64_func_sym + 2
- .word 0x1004
+ .word 14
.globl code_map_count
code_map_count = 2
>From 0c45ad65d02145f7d403d41aa57d2914b9fb479d Mon Sep 17 00:00:00 2001
From: Jacek Caban <jacek at codeweavers.com>
Date: Thu, 8 Jun 2023 22:59:53 +0200
Subject: [PATCH 4/4] [lld] Add support for EC code map.
---
lld/COFF/Chunks.cpp | 14 +++++
lld/COFF/Chunks.h | 21 +++++++
lld/COFF/Driver.cpp | 5 ++
lld/COFF/Writer.cpp | 66 ++++++++++++++++++++++
lld/test/COFF/Inputs/loadconfig-arm64ec.s | 4 +-
lld/test/COFF/arm64ec-codemap.test | 68 ++++++-----------------
6 files changed, 124 insertions(+), 54 deletions(-)
diff --git a/lld/COFF/Chunks.cpp b/lld/COFF/Chunks.cpp
index 4e845afa8947a5f..39f4575031be549 100644
--- a/lld/COFF/Chunks.cpp
+++ b/lld/COFF/Chunks.cpp
@@ -896,6 +896,20 @@ void RVAFlagTableChunk::writeTo(uint8_t *buf) const {
"RVA tables should be de-duplicated");
}
+size_t ECCodeMapChunk::getSize() const {
+ return map.size() * sizeof(chpe_range_entry);
+}
+
+void ECCodeMapChunk::writeTo(uint8_t *buf) const {
+ auto table = reinterpret_cast<chpe_range_entry *>(buf);
+ for (uint32_t i = 0; i < map.size(); i++) {
+ const ECCodeMapEntry &entry = map[i];
+ uint32_t start = entry.first->getRVA();
+ table[i].StartOffset = start | entry.type;
+ table[i].Length = entry.last->getRVA() + entry.last->getSize() - start;
+ }
+}
+
// MinGW specific, for the "automatic import of variables from DLLs" feature.
size_t PseudoRelocTableChunk::getSize() const {
if (relocs.empty())
diff --git a/lld/COFF/Chunks.h b/lld/COFF/Chunks.h
index 156e7a807cb8fd7..7b6bdeae4234ef5 100644
--- a/lld/COFF/Chunks.h
+++ b/lld/COFF/Chunks.h
@@ -703,6 +703,27 @@ class EmptyChunk : public NonSectionChunk {
void writeTo(uint8_t *buf) const override {}
};
+class ECCodeMapEntry {
+public:
+ ECCodeMapEntry(Chunk *first, Chunk *last, chpe_range_type type)
+ : first(first), last(last), type(type) {}
+ Chunk *first;
+ Chunk *last;
+ chpe_range_type type;
+};
+
+// This is a chunk containing CHPE code map on EC targets. It's a table
+// of address ranges and their types.
+class ECCodeMapChunk : public NonSectionChunk {
+public:
+ ECCodeMapChunk(std::vector<ECCodeMapEntry> &map) : map(map) {}
+ size_t getSize() const override;
+ void writeTo(uint8_t *buf) const override;
+
+private:
+ std::vector<ECCodeMapEntry> ↦
+};
+
// MinGW specific, for the "automatic import of variables from DLLs" feature.
// This provides the table of runtime pseudo relocations, for variable
// references that turned out to need to be imported from a DLL even though
diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp
index 5613c2e6993a5af..337b0e6bb0e99b2 100644
--- a/lld/COFF/Driver.cpp
+++ b/lld/COFF/Driver.cpp
@@ -2355,6 +2355,11 @@ void LinkerDriver::linkerMain(ArrayRef<const char *> argsArr) {
ctx.symtab.addAbsolute(mangle("__guard_eh_cont_count"), 0);
ctx.symtab.addAbsolute(mangle("__guard_eh_cont_table"), 0);
+ if (isArm64EC(config->machine)) {
+ ctx.symtab.addAbsolute("__hybrid_code_map", 0);
+ ctx.symtab.addAbsolute("__hybrid_code_map_count", 0);
+ }
+
if (config->pseudoRelocs) {
ctx.symtab.addAbsolute(mangle("__RUNTIME_PSEUDO_RELOC_LIST__"), 0);
ctx.symtab.addAbsolute(mangle("__RUNTIME_PSEUDO_RELOC_LIST_END__"), 0);
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index 960328d686852a3..4ff4b9412974aa1 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -221,6 +221,7 @@ class Writer {
uint16_t type, int margin);
bool createThunks(OutputSection *os, int margin);
bool verifyRanges(const std::vector<Chunk *> chunks);
+ void createECCodeMap();
void finalizeAddresses();
void removeEmptySections();
void assignOutputSectionIndices();
@@ -229,6 +230,7 @@ class Writer {
template <typename PEHeaderTy> void writeHeader();
void createSEHTable();
void createRuntimePseudoRelocs();
+ void createECChunks();
void insertCtorDtorSymbols();
void markSymbolsWithRelocations(ObjFile *file, SymbolRVASet &usedSymbols);
void createGuardCFTables();
@@ -271,6 +273,7 @@ class Writer {
std::map<PartialSectionKey, PartialSection *> partialSections;
std::vector<char> strtab;
std::vector<llvm::object::coff_symbol16> outputSymtab;
+ std::vector<ECCodeMapEntry> codeMap;
IdataContents idata;
Chunk *importTableStart = nullptr;
uint64_t importTableSize = 0;
@@ -528,6 +531,53 @@ bool Writer::createThunks(OutputSection *os, int margin) {
return addressesChanged;
}
+// Create a code map for CHPE metadata.
+void Writer::createECCodeMap() {
+ if (!isArm64EC(ctx.config.machine))
+ return;
+
+ // Clear the map in case we were're recomputing the map after adding
+ // a range extension thunk.
+ codeMap.clear();
+
+ std::optional<chpe_range_type> lastType;
+ Chunk *first, *last;
+
+ auto closeRange = [&]() {
+ if (lastType) {
+ codeMap.push_back({first, last, *lastType});
+ lastType.reset();
+ }
+ };
+
+ for (OutputSection *sec : ctx.outputSections) {
+ if (!sec->isCodeSection()) {
+ closeRange();
+ continue;
+ }
+
+ for (Chunk *c : sec->chunks) {
+ // Skip empty section chunks. MSVC does not seem to do that and
+ // generates empty code ranges in some cases.
+ if (isa<SectionChunk>(c) && !c->getSize())
+ continue;
+
+ std::optional<chpe_range_type> chunkType = c->getArm64ECRangeType();
+ if (chunkType != lastType) {
+ closeRange();
+ first = c;
+ lastType = chunkType;
+ }
+ last = c;
+ }
+ }
+
+ closeRange();
+
+ Symbol *tableCountSym = ctx.symtab.findUnderscore("__hybrid_code_map_count");
+ cast<DefinedAbsolute>(tableCountSym)->setVA(codeMap.size());
+}
+
// Verify that all relocations are in range, with no extra margin requirements.
bool Writer::verifyRanges(const std::vector<Chunk *> chunks) {
for (Chunk *c : chunks) {
@@ -1077,6 +1127,9 @@ void Writer::createMiscChunks() {
if (config->guardCF != GuardCFLevel::Off)
createGuardCFTables();
+ if (isArm64EC(config->machine))
+ createECChunks();
+
if (config->autoImport)
createRuntimePseudoRelocs();
@@ -1402,6 +1455,10 @@ void Writer::assignAddresses() {
llvm::TimeTraceScope timeScope("Assign addresses");
Configuration *config = &ctx.config;
+ // We need to create EC code map so that ECCodeMapChunk knows its size.
+ // We do it here to make sure that we account for range extension chunks.
+ createECCodeMap();
+
sizeOfHeaders = dosStubSize + sizeof(PEMagic) + sizeof(coff_file_header) +
sizeof(data_directory) * numberOfDataDirectory +
sizeof(coff_section) * ctx.outputSections.size();
@@ -1937,6 +1994,15 @@ void Writer::maybeAddRVATable(SymbolRVASet tableSymbols, StringRef tableSym,
cast<DefinedAbsolute>(c)->setVA(tableChunk->getSize() / (hasFlag ? 5 : 4));
}
+// Create CHPE metadata chunks.
+void Writer::createECChunks() {
+ auto codeMapChunk = make<ECCodeMapChunk>(codeMap);
+ rdataSec->addChunk(codeMapChunk);
+ Symbol *codeMapSym = ctx.symtab.findUnderscore("__hybrid_code_map");
+ replaceSymbol<DefinedSynthetic>(codeMapSym, codeMapSym->getName(),
+ codeMapChunk);
+}
+
// MinGW specific. Gather all relocations that are imported from a DLL even
// though the code didn't expect it to, produce the table that the runtime
// uses for fixing them up, and provide the synthetic symbols that the
diff --git a/lld/test/COFF/Inputs/loadconfig-arm64ec.s b/lld/test/COFF/Inputs/loadconfig-arm64ec.s
index 1efd02406ca691b..78ae594a21eff3f 100644
--- a/lld/test/COFF/Inputs/loadconfig-arm64ec.s
+++ b/lld/test/COFF/Inputs/loadconfig-arm64ec.s
@@ -64,8 +64,8 @@ __os_arm64x_helper8:
.p2align 3, 0
__chpe_metadata:
.word 1
- .rva code_map
- .word code_map_count
+ .rva __hybrid_code_map
+ .word __hybrid_code_map_count
.word 0 // __x64_code_ranges_to_entry_points
.word 0 //__arm64x_redirection_metadata
.rva __os_arm64x_dispatch_call_no_redirect
diff --git a/lld/test/COFF/arm64ec-codemap.test b/lld/test/COFF/arm64ec-codemap.test
index 131644c4983ca3d..ce4034847f82762 100644
--- a/lld/test/COFF/arm64ec-codemap.test
+++ b/lld/test/COFF/arm64ec-codemap.test
@@ -3,16 +3,15 @@ RUN: split-file %s %t.dir && cd %t.dir
RUN: llvm-mc -filetype=obj -triple=arm64-windows arm64-func-sym.s -o arm64-func-sym.obj
RUN: llvm-mc -filetype=obj -triple=arm64ec-windows arm64ec-func-sym.s -o arm64ec-func-sym.obj
+RUN: llvm-mc -filetype=obj -triple=arm64ec-windows empty-sec.s -o arm64ec-empty-sec.obj
RUN: llvm-mc -filetype=obj -triple=x86_64-windows x86_64-func-sym.s -o x86_64-func-sym.obj
-RUN: llvm-mc -filetype=obj -triple=arm64ec-windows codemap.s -o codemap.obj
-RUN: llvm-mc -filetype=obj -triple=arm64ec-windows codemap2.s -o codemap2.obj
-RUN: llvm-mc -filetype=obj -triple=arm64ec-windows codemap3.s -o codemap3.obj
+RUN: llvm-mc -filetype=obj -triple=x86_64-windows empty-sec.s -o x86_64-empty-sec.obj
RUN: llvm-mc -filetype=obj -triple=arm64ec-windows %S/Inputs/loadconfig-arm64ec.s -o loadconfig-arm64ec.obj
Link ARM64EC DLL and verify that the code is arranged as expected.
RUN: lld-link -out:test.dll -machine:arm64ec arm64ec-func-sym.obj x86_64-func-sym.obj \
-RUN: codemap.obj loadconfig-arm64ec.obj -dll -noentry
+RUN: loadconfig-arm64ec.obj -dll -noentry
RUN: llvm-readobj --coff-load-config test.dll | FileCheck -check-prefix=CODEMAP %s
CODEMAP: CodeMap [
@@ -44,12 +43,18 @@ DISASM-NEXT: 180006005: c3 retq
Order of arguments doesn't matter in this case, chunks are sorted by target type anyway.
RUN: lld-link -out:test2.dll -machine:arm64ec x86_64-func-sym.obj arm64ec-func-sym.obj \
-RUN: codemap.obj loadconfig-arm64ec.obj -dll -noentry
+RUN: loadconfig-arm64ec.obj -dll -noentry
RUN: llvm-readobj --coff-load-config test2.dll | FileCheck -check-prefix=CODEMAP %s
RUN: llvm-objdump -d test2.dll | FileCheck -check-prefix=DISASM %s
RUN: lld-link -out:testx.dll -machine:arm64x arm64-func-sym.obj arm64ec-func-sym.obj \
-RUN: x86_64-func-sym.obj codemap2.obj loadconfig-arm64ec.obj -dll -noentry
+RUN: x86_64-func-sym.obj loadconfig-arm64ec.obj -dll -noentry
+
+Adding empty chunks does not affect code map ranges.
+
+RUN: lld-link -out:test3.dll -machine:arm64ec x86_64-empty-sec.obj arm64ec-empty-sec.obj \
+RUN: arm64ec-func-sym.obj x86_64-func-sym.obj loadconfig-arm64ec.obj -dll -noentry
+RUN: llvm-readobj --coff-load-config test3.dll | FileCheck -check-prefix=CODEMAP %s
Do the same with ARM64X target.
@@ -87,7 +92,7 @@ DISASMX-NEXT: 180007005: c3 retq
Test merged sections.
RUN: lld-link -out:testm.dll -machine:arm64ec arm64ec-func-sym.obj x86_64-func-sym.obj \
-RUN: codemap3.obj loadconfig-arm64ec.obj -dll -noentry -merge:test=.text
+RUN: loadconfig-arm64ec.obj -dll -noentry -merge:test=.text
RUN: llvm-readobj --coff-load-config testm.dll | FileCheck -check-prefix=CODEMAPM %s
CODEMAPM: CodeMap [
@@ -186,48 +191,7 @@ x86_64_func_sym2:
.section .testdata, "rd"
.xword 1
-#--- codemap.s
- .section .rdata,"dr"
- .globl code_map
-code_map:
- .rva arm64ec_func_sym + 1
- .word 8
- .rva x86_64_func_sym + 2
- .word 6
- .rva arm64ec_func_sym2 + 1
- .word 8
- .rva x86_64_func_sym2 + 2
- .word 6
-
- .globl code_map_count
-code_map_count = 4
-
-#--- codemap2.s
- .section .rdata,"dr"
- .globl code_map
-code_map:
- .rva arm64_func_sym
- .word 8
- .rva arm64ec_func_sym + 1
- .word 8
- .rva x86_64_func_sym + 2
- .word 6
- .rva arm64ec_func_sym2 + 1
- .word 8
- .rva x86_64_func_sym2 + 2
- .word 6
-
- .globl code_map_count
-code_map_count = 5
-
-#--- codemap3.s
- .section .rdata,"dr"
- .globl code_map
-code_map:
- .rva arm64ec_func_sym + 1
- .word 16
- .rva x86_64_func_sym + 2
- .word 14
-
- .globl code_map_count
-code_map_count = 2
+#--- empty-sec.s
+ .section .empty1, "xr"
+ .section .empty2, "xr"
+ .section .empty3, "xr"
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