[llvm] cc6f9cf - [RISCV] Add zbb coverage to test file [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 30 13:18:48 PDT 2023
Author: Philip Reames
Date: 2023-10-30T13:18:35-07:00
New Revision: cc6f9cf5a2d5c246f30b74f748ee9a355e49d22a
URL: https://github.com/llvm/llvm-project/commit/cc6f9cf5a2d5c246f30b74f748ee9a355e49d22a
DIFF: https://github.com/llvm/llvm-project/commit/cc6f9cf5a2d5c246f30b74f748ee9a355e49d22a.diff
LOG: [RISCV] Add zbb coverage to test file [nfc]
Added:
Modified:
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
index 6be6785fc1d0eee..98488c9a589a3a8 100644
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -2,7 +2,9 @@
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64I
+; RUN: | FileCheck %s -check-prefixes=RV64,RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBB
define i8 @sext_i1_to_i8(i1 %a) nounwind {
; RV32I-LABEL: sext_i1_to_i8:
@@ -11,11 +13,11 @@ define i8 @sext_i1_to_i8(i1 %a) nounwind {
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_i1_to_i8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 63
-; RV64I-NEXT: srai a0, a0, 63
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_i1_to_i8:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%1 = sext i1 %a to i8
ret i8 %1
}
@@ -27,11 +29,11 @@ define i16 @sext_i1_to_i16(i1 %a) nounwind {
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_i1_to_i16:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 63
-; RV64I-NEXT: srai a0, a0, 63
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_i1_to_i16:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%1 = sext i1 %a to i16
ret i16 %1
}
@@ -43,11 +45,11 @@ define i32 @sext_i1_to_i32(i1 %a) nounwind {
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_i1_to_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 63
-; RV64I-NEXT: srai a0, a0, 63
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_i1_to_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%1 = sext i1 %a to i32
ret i32 %1
}
@@ -60,11 +62,11 @@ define i64 @sext_i1_to_i64(i1 %a) nounwind {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_i1_to_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 63
-; RV64I-NEXT: srai a0, a0, 63
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_i1_to_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%1 = sext i1 %a to i64
ret i64 %1
}
@@ -81,6 +83,11 @@ define i16 @sext_i8_to_i16(i8 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sext_i8_to_i16:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.b a0, a0
+; RV64ZBB-NEXT: ret
%1 = sext i8 %a to i16
ret i16 %1
}
@@ -97,6 +104,11 @@ define i32 @sext_i8_to_i32(i8 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sext_i8_to_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.b a0, a0
+; RV64ZBB-NEXT: ret
%1 = sext i8 %a to i32
ret i32 %1
}
@@ -114,6 +126,11 @@ define i64 @sext_i8_to_i64(i8 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sext_i8_to_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.b a0, a0
+; RV64ZBB-NEXT: ret
%1 = sext i8 %a to i64
ret i64 %1
}
@@ -130,6 +147,11 @@ define i32 @sext_i16_to_i32(i16 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sext_i16_to_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.h a0, a0
+; RV64ZBB-NEXT: ret
%1 = sext i16 %a to i32
ret i32 %1
}
@@ -147,6 +169,11 @@ define i64 @sext_i16_to_i64(i16 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sext_i16_to_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: sext.h a0, a0
+; RV64ZBB-NEXT: ret
%1 = sext i16 %a to i64
ret i64 %1
}
@@ -157,10 +184,10 @@ define i64 @sext_i32_to_i64(i32 %a) nounwind {
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_i32_to_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_i32_to_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: ret
%1 = sext i32 %a to i64
ret i64 %1
}
@@ -171,10 +198,10 @@ define i8 @zext_i1_to_i8(i1 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i1_to_i8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i1_to_i8:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1
+; RV64-NEXT: ret
%1 = zext i1 %a to i8
ret i8 %1
}
@@ -185,10 +212,10 @@ define i16 @zext_i1_to_i16(i1 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i1_to_i16:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i1_to_i16:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1
+; RV64-NEXT: ret
%1 = zext i1 %a to i16
ret i16 %1
}
@@ -199,10 +226,10 @@ define i32 @zext_i1_to_i32(i1 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i1_to_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i1_to_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1
+; RV64-NEXT: ret
%1 = zext i1 %a to i32
ret i32 %1
}
@@ -214,10 +241,10 @@ define i64 @zext_i1_to_i64(i1 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i1_to_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i1_to_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1
+; RV64-NEXT: ret
%1 = zext i1 %a to i64
ret i64 %1
}
@@ -228,10 +255,10 @@ define i16 @zext_i8_to_i16(i8 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i8_to_i16:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i8_to_i16:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 255
+; RV64-NEXT: ret
%1 = zext i8 %a to i16
ret i16 %1
}
@@ -242,10 +269,10 @@ define i32 @zext_i8_to_i32(i8 %a) nounwind {
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i8_to_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i8_to_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 255
+; RV64-NEXT: ret
%1 = zext i8 %a to i32
ret i32 %1
}
@@ -257,10 +284,10 @@ define i64 @zext_i8_to_i64(i8 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i8_to_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 255
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i8_to_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 255
+; RV64-NEXT: ret
%1 = zext i8 %a to i64
ret i64 %1
}
@@ -277,6 +304,11 @@ define i32 @zext_i16_to_i32(i16 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: zext_i16_to_i32:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: zext.h a0, a0
+; RV64ZBB-NEXT: ret
%1 = zext i16 %a to i32
ret i32 %1
}
@@ -294,6 +326,11 @@ define i64 @zext_i16_to_i64(i16 %a) nounwind {
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: zext_i16_to_i64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: zext.h a0, a0
+; RV64ZBB-NEXT: ret
%1 = zext i16 %a to i64
ret i64 %1
}
@@ -304,11 +341,11 @@ define i64 @zext_i32_to_i64(i32 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_i32_to_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: ret
+; RV64-LABEL: zext_i32_to_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: ret
%1 = zext i32 %a to i64
ret i64 %1
}
@@ -318,9 +355,9 @@ define i1 @trunc_i8_to_i1(i8 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i8_to_i1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i8_to_i1:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i8 %a to i1
ret i1 %1
}
@@ -330,9 +367,9 @@ define i1 @trunc_i16_to_i1(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i16_to_i1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i16_to_i1:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i16 %a to i1
ret i1 %1
}
@@ -342,9 +379,9 @@ define i1 @trunc_i32_to_i1(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i32_to_i1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i32_to_i1:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i32 %a to i1
ret i1 %1
}
@@ -354,9 +391,9 @@ define i1 @trunc_i64_to_i1(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i64_to_i1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i64_to_i1:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i64 %a to i1
ret i1 %1
}
@@ -366,9 +403,9 @@ define i8 @trunc_i16_to_i8(i16 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i16_to_i8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i16_to_i8:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i16 %a to i8
ret i8 %1
}
@@ -378,9 +415,9 @@ define i8 @trunc_i32_to_i8(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i32_to_i8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i32_to_i8:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i32 %a to i8
ret i8 %1
}
@@ -390,9 +427,9 @@ define i8 @trunc_i64_to_i8(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i64_to_i8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i64_to_i8:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i64 %a to i8
ret i8 %1
}
@@ -402,9 +439,9 @@ define i16 @trunc_i32_to_i16(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i32_to_i16:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i32_to_i16:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i32 %a to i16
ret i16 %1
}
@@ -414,9 +451,9 @@ define i16 @trunc_i64_to_i16(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i64_to_i16:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i64_to_i16:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i64 %a to i16
ret i16 %1
}
@@ -426,9 +463,9 @@ define i32 @trunc_i64_to_i32(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: trunc_i64_to_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
+; RV64-LABEL: trunc_i64_to_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: ret
%1 = trunc i64 %a to i32
ret i32 %1
}
@@ -441,11 +478,11 @@ define i32 @sext_of_not_i32(i1 %x) {
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_of_not_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_of_not_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%xor = xor i1 %x, 1
%sext = sext i1 %xor to i32
ret i32 %sext
@@ -459,11 +496,11 @@ define i64 @sext_of_not_i64(i1 %x) {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_of_not_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: andi a0, a0, 1
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_of_not_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: andi a0, a0, 1
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%xor = xor i1 %x, 1
%sext = sext i1 %xor to i64
ret i64 %sext
@@ -478,13 +515,13 @@ define i32 @sext_of_not_cmp_i32(i32 %x) {
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_of_not_cmp_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, -7
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_of_not_cmp_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%cmp = icmp eq i32 %x, 7
%xor = xor i1 %cmp, 1
%sext = sext i1 %xor to i32
@@ -501,12 +538,12 @@ define i64 @sext_of_not_cmp_i64(i64 %x) {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: sext_of_not_cmp_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -7
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
+; RV64-LABEL: sext_of_not_cmp_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%cmp = icmp eq i64 %x, 7
%xor = xor i1 %cmp, 1
%sext = sext i1 %xor to i64
@@ -522,13 +559,13 @@ define i32 @dec_of_zexted_cmp_i32(i32 %x) {
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: dec_of_zexted_cmp_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: addi a0, a0, -7
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
+; RV64-LABEL: dec_of_zexted_cmp_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: sext.w a0, a0
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%cmp = icmp eq i32 %x, 7
%zext = zext i1 %cmp to i32
%dec = sub i32 %zext, 1
@@ -545,12 +582,12 @@ define i64 @dec_of_zexted_cmp_i64(i64 %x) {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: dec_of_zexted_cmp_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -7
-; RV64I-NEXT: seqz a0, a0
-; RV64I-NEXT: addi a0, a0, -1
-; RV64I-NEXT: ret
+; RV64-LABEL: dec_of_zexted_cmp_i64:
+; RV64: # %bb.0:
+; RV64-NEXT: addi a0, a0, -7
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: ret
%cmp = icmp eq i64 %x, 7
%zext = zext i1 %cmp to i64
%dec = sub i64 %zext, 1
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