[llvm] [RISCV] Add _RM pseudos to pseudos table (PR #70693)
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Mon Oct 30 10:17:34 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
I noticed that some _RM vector pseudos still had IMPLICIT_DEFs in their merge
operands. This was because they didn't have RISCVVPseudo entries, and so
doPeepholeNoRegPassThru in RISCVISelDAGToDAG skipped over them.
This adds RISCVVPseudo to them so that they are picked up by
doPeepholeNoRegPassthru.
The only remaining vector pseudo that doesn't have an entry is
PseudoVFROUND_NOEXCEPT. It expands out to several vector instructions though so
I'm not sure what its BaseInstr would be.
---
Full diff: https://github.com/llvm/llvm-project/pull/70693.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+6-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll (+40-44)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 445f057d61ee1dc..bec67153b6543d4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -134,7 +134,8 @@ class PseudoToVInst<string PseudoInst> {
["_M2", ""],
["_M4", ""],
["_M8", ""],
- ["_SE", ""]
+ ["_SE", ""],
+ ["_RM", ""]
];
string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst,
!subst(AffixSubst[0], AffixSubst[1], Acc));
@@ -1113,7 +1114,8 @@ class VPseudoUnaryNoMask_FRM<VReg RetClass,
string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2, ixlenimm:$frm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
+ AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
@@ -1131,7 +1133,8 @@ class VPseudoUnaryMask_FRM<VReg RetClass,
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm,
- AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
+ AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
+ RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index 9c30d3ac71679ba..e62eec573a57040 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -529,16 +529,15 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind {
;
; LMULMAX2-RV32F-LABEL: ctlz_v2i64:
; LMULMAX2-RV32F: # %bb.0:
-; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8
-; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: li a1, 190
-; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV32F-NEXT: fsrm a1
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8
; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
@@ -550,12 +549,12 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind {
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v9, v8
-; LMULMAX2-RV64F-NEXT: fsrm a1
-; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV64F-NEXT: fsrm a1
+; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: li a1, 64
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
@@ -1129,16 +1128,15 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
;
; LMULMAX2-RV32F-LABEL: ctlz_v4i64:
; LMULMAX2-RV32F: # %bb.0:
-; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: li a1, 190
-; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1
+; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v12, v8
+; LMULMAX2-RV32F-NEXT: fsrm a1
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v12, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8
; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
@@ -1150,16 +1148,16 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV64F-NEXT: li a1, 190
+; LMULMAX2-RV64F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v11, v8
; LMULMAX2-RV64F-NEXT: fsrm a1
-; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
-; LMULMAX2-RV64F-NEXT: li a1, 190
-; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
-; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
+; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v11, 23
+; LMULMAX2-RV64F-NEXT: vwsubu.vv v12, v10, v8
; LMULMAX2-RV64F-NEXT: li a1, 64
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; LMULMAX2-RV64F-NEXT: vminu.vx v8, v10, a1
+; LMULMAX2-RV64F-NEXT: vminu.vx v8, v12, a1
; LMULMAX2-RV64F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: ret
;
@@ -1716,16 +1714,15 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
;
; LMULMAX2-RV32F-LABEL: ctlz_zero_undef_v2i64:
; LMULMAX2-RV32F: # %bb.0:
-; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8
-; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: li a1, 190
-; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV32F-NEXT: fsrm a1
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8
; LMULMAX2-RV32F-NEXT: vse64.v v9, (a0)
; LMULMAX2-RV32F-NEXT: ret
@@ -1734,12 +1731,12 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v9, v8
-; LMULMAX2-RV64F-NEXT: fsrm a1
-; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV64F-NEXT: fsrm a1
+; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: vse64.v v10, (a0)
; LMULMAX2-RV64F-NEXT: ret
@@ -2286,16 +2283,15 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
;
; LMULMAX2-RV32F-LABEL: ctlz_zero_undef_v4i64:
; LMULMAX2-RV32F: # %bb.0:
-; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: li a1, 190
-; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1
+; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v12, v8
+; LMULMAX2-RV32F-NEXT: fsrm a1
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v12, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8
; LMULMAX2-RV32F-NEXT: vse64.v v10, (a0)
; LMULMAX2-RV32F-NEXT: ret
@@ -2304,14 +2300,14 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
+; LMULMAX2-RV64F-NEXT: li a1, 190
+; LMULMAX2-RV64F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v11, v8
; LMULMAX2-RV64F-NEXT: fsrm a1
-; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
-; LMULMAX2-RV64F-NEXT: li a1, 190
-; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
-; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
-; LMULMAX2-RV64F-NEXT: vse64.v v10, (a0)
+; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v11, 23
+; LMULMAX2-RV64F-NEXT: vwsubu.vv v12, v10, v8
+; LMULMAX2-RV64F-NEXT: vse64.v v12, (a0)
; LMULMAX2-RV64F-NEXT: ret
;
; LMULMAX2-RV32D-LABEL: ctlz_zero_undef_v4i64:
``````````
</details>
https://github.com/llvm/llvm-project/pull/70693
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