[llvm] [DAG] Canonicalize zero_extend to sign_extend based on target preference (PR #70671)
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Mon Oct 30 08:44:31 PDT 2023
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git-clang-format --diff 56dab2cb0733f10df4e9cff8c83dd7081154527b d19c0c56fb97ed9c248e9f6182419a078c1f5761 -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3f186a71256d..3e2fda23160c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13833,7 +13833,6 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0);
-
// (zext (shl (zext x), cst)) -> (shl (zext x), cst)
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
!TLI.isZExtFree(N0, VT)) {
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https://github.com/llvm/llvm-project/pull/70671
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