[llvm] [RISCV] Select atomic_{load/store} to pseudos and expand them later (PR #67108)

Wang Pengcheng via llvm-commits llvm-commits at lists.llvm.org
Sun Oct 22 22:44:08 PDT 2023


wangpc-pp wrote:

> Oh, and was #69685 just an opportune moment to re-advertise this patch - or did you see that work interacting with this change in some way? if so, could you elaborate please? Many thanks.

`Zalasr` extension provide instructions for atomic load/store (for example, `load acquire` and `store release`). If we are going to support CodeGen of this extension, then we shouldn't expand them before ISel, or the patterns may not be matched because we may insert some LLVM IRs between `fence` instruction and load/store (and we may not be able to describe the patterns in TableGen). For AArch64, this kind of atomic load/store instructions will be selected just like the way in this PR (actually, this PR is inspired by AArch64 target :-)), except that they are selected to actual instructions instead of pseudos.

Fused atomic load/store are just like `Zalasr` extension, except the addressing mode (`Zalasr` supports zero offset address only, while fused atomic load/store can be like normal load/store instructions). The fused version of atomic load/store is just a workaround since RISCV is lack of such instructions, while `Zalasr` has fill the hole.

Before this PR, the lowering path of atomic load/store is:
```
atomic load/store (LLVM IR) -> *Expand Atomic instructions Pass* -> monotonic load/store with leading/trailing fence (LLVM IR) -> SDAG -> *ISel* -> normal load/store instructions with leading/trailing fence
```
After this PR, it will be like:
```
atomic load/store (LLVM IR) -> SDAG -> *ISel* -> pseudo atomic load/store -> *RISC-V atomic pseudo instruction expansion pass* -> normal load/store instructions with leading/trailing fence
```
If `Zalasr` is enabled, then we can expand pseudo atomic load/store to instructions in `Zalasr` instead of normal load/store instructions with leading/trailing fence.

I don't know if the above statement has made my intention of this PR clearer, let me know if there are any questions. :-)
CC @jrtc27

https://github.com/llvm/llvm-project/pull/67108


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