[llvm] [RISCV] Reorder the vector register allocation sequence. (PR #69290)

[Brandon Wu via llvm-commits]

4vtomat wrote:

Currently the vector calling convention proposal reserves `15` vregs for callee-saved registers(`v1-v7`, `v24-v31`). If this change happens, maybe the number of callee-saved registers would be changed to 16, something like `v16-v31`. 
Also the algorithm for vector and tuple type arguments need some changes as well.
But I guess it needs more evaluation and discussion.

https://github.com/llvm/llvm-project/pull/69290