[llvm] 3d40411 - [AMDGPU] Set size to all SOP pseudos (#69756)

[via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2023-10-22T00:33:45-07:00
New Revision: 3d40411ee88958864316ff9afb23ec2d0166b285

URL: https://github.com/llvm/llvm-project/commit/3d40411ee88958864316ff9afb23ec2d0166b285
DIFF: https://github.com/llvm/llvm-project/commit/3d40411ee88958864316ff9afb23ec2d0166b285.diff

LOG: [AMDGPU] Set size to all SOP pseudos (#69756)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SOPInstructions.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index f3309049e7a7fd9..2f3b0ff2f76215e 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -15,6 +15,7 @@ class SOP_Pseudo<string opName, dag outs, dag ins, string asmOps,
 
   let isPseudo = 1;
   let isCodeGenOnly = 1;
+  let Size = 4;
 
   string Mnemonic = opName;
   string AsmOperands = asmOps;
@@ -36,7 +37,6 @@ class SOP1_Pseudo <string opName, dag outs, dag ins,
   let SALU = 1;
   let SOP1 = 1;
   let SchedRW = [WriteSALU];
-  let Size = 4;
   let UseNamedOperandTable = 1;
 
   bits<1> has_src0 = 1;
@@ -455,7 +455,6 @@ class SOP2_Pseudo<string opName, dag outs, dag ins,
   // let sdst = xxx in {
   // for multiclasses that include both real and pseudo instructions.
   // field bits<7> sdst = 0;
-  // let Size = 4; // Do we need size here?
 }
 
 class SOP2_Real<SOP_Pseudo ps, string real_name = ps.Mnemonic> :