[llvm] [RISCV][GISel] Add instruction selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions. (PR #69808)

[via llvm-commits]

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@@ -198,6 +199,16 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
 
   getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
 
+  // FP Operations
+
+  if (ST.hasStdExtF()) {
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tschuett wrote:

X86 has also a fleet of extensions, but RISC-V will probably win. They do it slightly different:
https://github.com/llvm/llvm-project/blob/af447dde5e723e925b9c8fdc6715b07f0caf6161/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp#L420

https://github.com/llvm/llvm-project/pull/69808