[llvm] [RISCV][GISel] Add regbank selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions. (PR #69805)

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git-clang-format --diff 3b5d59ab55f885f1e12a9d306de351b798552426 774f770a7bff160f78b1c3f3af1fb0ca9a638866 -- llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index fe55cbf7b07a..39a183ca6091 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -180,8 +180,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_FDIV: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
     OperandsMapping = Ty.getSizeInBits() == 64
-                           ? &RISCV::ValueMappings[RISCV::FPR64Idx]
-                           : &RISCV::ValueMappings[RISCV::FPR32Idx];
+                          ? &RISCV::ValueMappings[RISCV::FPR64Idx]
+                          : &RISCV::ValueMappings[RISCV::FPR32Idx];
     break;
   }
   default:

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https://github.com/llvm/llvm-project/pull/69805