[llvm] [ARM] Add a method to clear registers (PR #69659)
Bill Wendling via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 20 15:25:48 PDT 2023
https://github.com/bwendling updated https://github.com/llvm/llvm-project/pull/69659
>From 52667928de837bcd8cb1b90d5e123b01505a3e03 Mon Sep 17 00:00:00 2001
From: Bill Wendling <morbo at google.com>
Date: Wed, 18 Oct 2023 14:05:47 -0700
Subject: [PATCH 1/3] [ARM] Add a method to clear registers
This allows us to clear registers in target-independent code. The first
use will be for clearing the stack protector from registers before
returning.
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 ++++++++++
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 5 +++++
2 files changed, 15 insertions(+)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 1ffdde0360cf623..a07504aaedbc4da 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6735,6 +6735,16 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
return CallPt;
}
+void ARMBaseInstrInfo::buildClearRegister(Register DstReg,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator Iter,
+ DebugLoc &DL,
+ bool AllowSideEffects) const {
+ unsigned Opc = Subtarget.isThumb2() ? ARM::t2MOVi32imm : ARM::MOVi32imm;
+ BuildMI(MBB, Iter, DL, get(Opc), DstReg)
+ .addImm(0);
+}
+
bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(
MachineFunction &MF) const {
return Subtarget.isMClass() && MF.getFunction().hasMinSize();
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 5efcc1a0d9fc073..44b3e528c0c242e 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -363,6 +363,11 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
MachineBasicBlock::iterator &It, MachineFunction &MF,
outliner::Candidate &C) const override;
+ void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator Iter,
+ DebugLoc &DL,
+ bool AllowSideEffects = true) const override;
+
/// Enable outlining by default at -Oz.
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
>From 8c23c267e5a119695079b3153b938262270b8719 Mon Sep 17 00:00:00 2001
From: Bill Wendling <morbo at google.com>
Date: Thu, 19 Oct 2023 17:31:36 -0700
Subject: [PATCH 2/3] Reformat
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 3 +--
llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index a07504aaedbc4da..1add88dc01ea56e 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6741,8 +6741,7 @@ void ARMBaseInstrInfo::buildClearRegister(Register DstReg,
DebugLoc &DL,
bool AllowSideEffects) const {
unsigned Opc = Subtarget.isThumb2() ? ARM::t2MOVi32imm : ARM::MOVi32imm;
- BuildMI(MBB, Iter, DL, get(Opc), DstReg)
- .addImm(0);
+ BuildMI(MBB, Iter, DL, get(Opc), DstReg).addImm(0);
}
bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 44b3e528c0c242e..e65e684c562028c 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -364,8 +364,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
outliner::Candidate &C) const override;
void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator Iter,
- DebugLoc &DL,
+ MachineBasicBlock::iterator Iter, DebugLoc &DL,
bool AllowSideEffects = true) const override;
/// Enable outlining by default at -Oz.
>From 2e74597e37ac8745e652f67f28e4c8f27df3e558 Mon Sep 17 00:00:00 2001
From: Bill Wendling <morbo at google.com>
Date: Fri, 20 Oct 2023 15:22:43 -0700
Subject: [PATCH 3/3] Clear out floating point registers.
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 23 +++++++++++++++++++++--
llvm/lib/Target/ARM/ARMRegisterInfo.td | 6 ++++++
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 1add88dc01ea56e..69b2fdb01951a53 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -6740,8 +6740,27 @@ void ARMBaseInstrInfo::buildClearRegister(Register DstReg,
MachineBasicBlock::iterator Iter,
DebugLoc &DL,
bool AllowSideEffects) const {
- unsigned Opc = Subtarget.isThumb2() ? ARM::t2MOVi32imm : ARM::MOVi32imm;
- BuildMI(MBB, Iter, DL, get(Opc), DstReg).addImm(0);
+ assert(Register::isPhysicalRegister(DstReg) &&
+ "Can only clear physical registers");
+ const MachineFunction &MF = *MBB.getParent();
+ const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
+ const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+
+ if (TRI.isGeneralPurposeRegister(MF, DstReg)) {
+ unsigned Opc = Subtarget.isThumb() ? ARM::t2MOVi32imm : ARM::MOVi32imm;
+ BuildMI(MBB, Iter, DL, get(Opc), DstReg).addImm(0);
+ } else if (ARM::DPRRegClass.contains(DstReg)) {
+ // f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, and v4bf16 registers.
+ BuildMI(MBB, Iter, DL, get(ARM::FCONSTD), DstReg).addImm(0);
+ } else if (ARM::SPRRegClass.contains(DstReg)) {
+ // f32 registers.
+ BuildMI(MBB, Iter, DL, get(ARM::FCONSTS), DstReg).addImm(0);
+ } else if (ARM::HPRRegClass.contains(DstReg)) {
+ // f16 and bf16 registers.
+ BuildMI(MBB, Iter, DL, get(ARM::FCONSTH), DstReg).addImm(0);
+ }
+
+ llvm_unreachable("Unsupported register class");
}
bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
index 194d65cad8d1706..0eef81db3121a57 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -628,3 +628,9 @@ def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;
// FP context payload
def FPCXTRegs : RegisterClass<"ARM", [i32], 32, (add FPCXTNS)>;
+
+//===----------------------------------------------------------------------===//
+// Register categories.
+//
+
+def GeneralPurposeRegisters : RegisterCategory<[GPR]>;
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