[llvm] [RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (PR #69788)

[Luke Lau via llvm-commits]

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@@ -611,11 +607,10 @@ define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
 ; CHECK-LABEL: vreduce_fwadd_v32f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
 ; CHECK-NEXT:    vle16.v v8, (a0)
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lukel97 wrote:

Interesting side effect I didn't expect: This changes the VTYPE of unit-stride loads since they don't use LMUL, just the SEW/LMUL ratio. 

https://github.com/llvm/llvm-project/pull/69788