[llvm] dbc1b71 - [RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU… (#69409)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 20 14:49:05 PDT 2023
Author: Michael Maitland
Date: 2023-10-20T17:49:00-04:00
New Revision: dbc1b71cf454d75d5f5265d2d1d2b2273c03d22a
URL: https://github.com/llvm/llvm-project/commit/dbc1b71cf454d75d5f5265d2d1d2b2273c03d22a
DIFF: https://github.com/llvm/llvm-project/commit/dbc1b71cf454d75d5f5265d2d1d2b2273c03d22a.diff
LOG: [RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU… (#69409)
…L based on instruction EEW
Vector Unit Stride Loads and stores EEW and EMUL depend on the EEW given
in the instruction name and the SEW from vtype. llvm-mca needs some help to correctly report
this information.
Added:
llvm/test/tools/llvm-mca/RISCV/vle-vse.s
Modified:
llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
index 16f9c113e29a915..708ebd78718c5b9 100644
--- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
+++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
@@ -185,6 +185,38 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
return SmallVector<UniqueInstrument>();
}
+static std::pair<uint8_t, uint8_t>
+getEEWAndEMULForUnitStrideLoadStore(unsigned Opcode, RISCVII::VLMUL LMUL,
+ uint8_t SEW) {
+ uint8_t EEW;
+ switch (Opcode) {
+ case RISCV::VLM_V:
+ case RISCV::VSM_V:
+ case RISCV::VLE8_V:
+ case RISCV::VSE8_V:
+ EEW = 8;
+ break;
+ case RISCV::VLE16_V:
+ case RISCV::VSE16_V:
+ EEW = 16;
+ break;
+ case RISCV::VLE32_V:
+ case RISCV::VSE32_V:
+ EEW = 32;
+ break;
+ case RISCV::VLE64_V:
+ case RISCV::VSE64_V:
+ EEW = 64;
+ break;
+ default:
+ llvm_unreachable("Opcode is not a vector unit stride load nor store");
+ }
+
+ uint8_t EMUL =
+ static_cast<uint8_t>(RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW));
+ return std::make_pair(EEW, EMUL);
+}
+
unsigned RISCVInstrumentManager::getSchedClassID(
const MCInstrInfo &MCII, const MCInst &MCI,
const llvm::SmallVector<Instrument *> &IVec) const {
@@ -214,12 +246,23 @@ unsigned RISCVInstrumentManager::getSchedClassID(
// or (Opcode, LMUL, SEW) if SEW instrument is active, and depends on LMUL
// and SEW, or (Opcode, LMUL, 0) if does not depend on SEW.
uint8_t SEW = SI ? SI->getSEW() : 0;
- // Check if it depends on LMUL and SEW
- const RISCVVInversePseudosTable::PseudoInfo *RVV =
- RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
- // Check if it depends only on LMUL
- if (!RVV)
- RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
+
+ const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr;
+ if (Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V ||
+ Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V ||
+ Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V ||
+ Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V ||
+ Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V) {
+ RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(LMUL);
+ auto [EEW, EMUL] = getEEWAndEMULForUnitStrideLoadStore(Opcode, VLMUL, SEW);
+ RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW);
+ } else {
+ // Check if it depends on LMUL and SEW
+ RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
+ // Check if it depends only on LMUL
+ if (!RVV)
+ RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
+ }
// Not a RVV instr
if (!RVV) {
diff --git a/llvm/test/tools/llvm-mca/RISCV/vle-vse.s b/llvm/test/tools/llvm-mca/RISCV/vle-vse.s
new file mode 100644
index 000000000000000..15b8f854c587657
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/vle-vse.s
@@ -0,0 +1,1249 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle8.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle8.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle16.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle16.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle32.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle32.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle64.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle64.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse8.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse8.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse16.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse16.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse32.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse32.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse64.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse64.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlm.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vlm.v v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vsm.v v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vsm.v v1, (a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 400
+# CHECK-NEXT: Total Cycles: 1084
+# CHECK-NEXT: Total uOps: 400
+
+# CHECK: Dispatch Width: 2
+# CHECK-NEXT: uOps Per Cycle: 0.37
+# CHECK-NEXT: IPC: 0.37
+# CHECK-NEXT: Block RThroughput: 848.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 8.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 16.00 * vle64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse8.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse16.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 1.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse32.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 4.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 8.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 16.00 * vse64.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 * vlm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 2.00 * vsm.v v1, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFive7FDiv
+# CHECK-NEXT: [1] - SiFive7IDiv
+# CHECK-NEXT: [2] - SiFive7PipeA
+# CHECK-NEXT: [3] - SiFive7PipeB
+# CHECK-NEXT: [4] - SiFive7PipeV
+# CHECK-NEXT: [5] - SiFive7VA
+# CHECK-NEXT: [6] - SiFive7VL
+# CHECK-NEXT: [7] - SiFive7VS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - 200.00 - 848.00 - 424.00 424.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 - 16.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 - 16.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 - 16.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 16.00 - 16.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 - 4.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 - 8.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 - 16.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 - 16.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse8.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse16.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 1.00 - - 1.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse32.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 4.00 - - 4.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 8.00 - - 8.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 16.00 - - 16.00 vse64.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - 2.00 - vlm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
+# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - 2.00 - - 2.00 vsm.v v1, (a0)
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