[llvm] [RISCV][VSETVLI] Prefer VTYPE for immediate known to be less than VLMAX (PR #69759)

[Luke Lau via llvm-commits]

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@@ -406,13 +406,13 @@ define <16 x i32> @zextload_v16i8_v16i32(ptr %x) {
 ; LMULMAX1-NEXT:    vslidedown.vi v11, v9, 8
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; LMULMAX1-NEXT:    vzext.vf4 v10, v11
-; LMULMAX1-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma
+; LMULMAX1-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
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lukel97 wrote:

Even though we know that AVL <= VLMAX and so VL won't be changed here, is this still valid per the spec? 

> When rs1=x0 and rd=x0, the instruction operates as if the current vector length in vl is used as the AVL, and the resulting value is written to vl, but not to a destination register. This form can only be used when VLMAX and hence vl is not actually changed by the new SEW/LMUL ratio. Use of the instruction with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Implementations may set vill in this case.

Since we're still changing the SEW/LMUL ratio and thus VLMAX, wouldn't this be enough to satisfy the "Use of the instruction with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved." clause?

https://github.com/llvm/llvm-project/pull/69759