[llvm] cfdafc1 - [RISCV][GISel] Support G_PTRTOINT and G_INTTOPTR (#69542)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 20 12:03:13 PDT 2023
Author: Craig Topper
Date: 2023-10-20T12:03:09-07:00
New Revision: cfdafc1e7035df15937a1e840347ffe14643a05e
URL: https://github.com/llvm/llvm-project/commit/cfdafc1e7035df15937a1e840347ffe14643a05e
DIFF: https://github.com/llvm/llvm-project/commit/cfdafc1e7035df15937a1e840347ffe14643a05e.diff
LOG: [RISCV][GISel] Support G_PTRTOINT and G_INTTOPTR (#69542)
Legalizer, register bank selection, and instruction selection.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 8f2f77c43b6a6cc..ab2125a3615f385 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -289,6 +289,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
switch (Opc) {
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_PTRTOINT:
+ case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 475d8d5e3c6c791..3aae38a7d18de98 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -122,6 +122,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
getActionDefinitionsBuilder(G_PTR_ADD)
.legalFor({{p0, XLenLLT}});
+ getActionDefinitionsBuilder(G_PTRTOINT)
+ .legalFor({{XLenLLT, p0}})
+ .clampScalar(0, XLenLLT, XLenLLT);
+
+ getActionDefinitionsBuilder(G_INTTOPTR)
+ .legalFor({{p0, XLenLLT}})
+ .clampScalar(1, XLenLLT, XLenLLT);
+
getActionDefinitionsBuilder(G_BRCOND)
.legalFor({XLenLLT})
.minScalar(0, XLenLLT);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index c8073199ade1bd3..4ede55fc8c54f68 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -126,6 +126,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_UREM:
case TargetOpcode::G_UMULH:
case TargetOpcode::G_PTR_ADD:
+ case TargetOpcode::G_PTRTOINT:
+ case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_SEXT:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
new file mode 100644
index 000000000000000..9a56020006b09c3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrtoint_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: ptrtoint_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s32) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoptr_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: inttoptr_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = COPY $x10
+ %1:gprb(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
new file mode 100644
index 000000000000000..4f8259e69553602
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrtoint_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: ptrtoint_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s64) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoptr_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: inttoptr_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir
new file mode 100644
index 000000000000000..074c5c2dda3779d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir
@@ -0,0 +1,131 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %0:_(s16) = G_TRUNC %1(s32)
+ %2:_(p0) = G_INTTOPTR %0(s16)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s8
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %0:_(s8) = G_TRUNC %1(s32)
+ %2:_(p0) = G_INTTOPTR %0(s8)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s1
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %0:_(s1) = G_TRUNC %1(s32)
+ %2:_(p0) = G_INTTOPTR %0(s1)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
+ %3:_(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %3(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s44
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: p0_s44
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
+ %0:_(s44) = G_TRUNC %3(s64)
+ %4:_(p0) = G_INTTOPTR %0(s44)
+ $x10 = COPY %4(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir
new file mode 100644
index 000000000000000..9fba2dd9629de23
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir
@@ -0,0 +1,125 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s16) = G_PTRTOINT %0(p0)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s8
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s8) = G_PTRTOINT %0(p0)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s1
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s1) = G_PTRTOINT %0(p0)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_PTRTOINT %0(p0)
+ %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
+ $x10 = COPY %2(s32)
+ $x11 = COPY %3(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: p0_s44
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s44
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s44) = G_PTRTOINT %0(p0)
+ %4:_(s32) = G_TRUNC %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir
new file mode 100644
index 000000000000000..cff8d36a203a095
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir
@@ -0,0 +1,153 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %0:_(s32) = G_TRUNC %1(s64)
+ %2:_(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %0:_(s16) = G_TRUNC %1(s64)
+ %2:_(p0) = G_INTTOPTR %0(s16)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s8
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %0:_(s8) = G_TRUNC %1(s64)
+ %2:_(p0) = G_INTTOPTR %0(s8)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s1
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %0:_(s1) = G_TRUNC %1(s64)
+ %2:_(p0) = G_INTTOPTR %0(s1)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s128
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: p0_s128
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %0:_(s128) = G_MERGE_VALUES %1(s64), %2(s64)
+ %3:_(p0) = G_INTTOPTR %0(s128)
+ $x10 = COPY %3(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s88
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: p0_s88
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %1:_(s64) = COPY $x10
+ %2:_(s64) = COPY $x11
+ %3:_(s128) = G_MERGE_VALUES %1(s64), %2(s64)
+ %0:_(s88) = G_TRUNC %3(s128)
+ %4:_(p0) = G_INTTOPTR %0(s88)
+ $x10 = COPY %4(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir
new file mode 100644
index 000000000000000..7299c5963146bc3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir
@@ -0,0 +1,145 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s16) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s8
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s8) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s1
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s1) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s128
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s128
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %1:_(s128) = G_PTRTOINT %0(p0)
+ %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128)
+ $x10 = COPY %2(s64)
+ $x11 = COPY %3(s64)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: p0_s88
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s88
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s88) = G_PTRTOINT %0(p0)
+ %4:_(s64) = G_TRUNC %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 6f8d76953de4fb7..1677c734eb9171e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -408,14 +408,54 @@ body: |
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s32)
- ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
- ; RV32I-NEXT: $x10 = COPY [[COPY2]](p0)
+ ; RV32I-NEXT: $x10 = COPY [[PTR_ADD]](p0)
; RV32I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(p0) = G_PTR_ADD %0, %1(s32)
- %3:_(p0) = COPY %2(p0)
- $x10 = COPY %3(p0)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: ptrtoint
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV32I-LABEL: name: ptrtoint
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV32I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0)
+ ; RV32I-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoprt
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV32I-LABEL: name: inttoprt
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32)
+ ; RV32I-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %1(p0)
PseudoRET implicit $x10
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index 26120f770413623..701f3d49ed85b65 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -429,14 +429,54 @@ body: |
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64)
- ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
- ; RV64I-NEXT: $x10 = COPY [[COPY2]](p0)
+ ; RV64I-NEXT: $x10 = COPY [[PTR_ADD]](p0)
; RV64I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(p0) = G_PTR_ADD %0, %1(s64)
- %3:_(p0) = COPY %2(p0)
- $x10 = COPY %3(p0)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: ptrtoint
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV64I-LABEL: name: ptrtoint
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV64I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s64) = G_PTRTOINT [[COPY]](p0)
+ ; RV64I-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoprt
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV64I-LABEL: name: inttoprt
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s64)
+ ; RV64I-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %1(p0)
PseudoRET implicit $x10
...
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