[llvm] [RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU… (PR #69409)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 19 20:29:31 PDT 2023
================
@@ -214,12 +246,24 @@ unsigned RISCVInstrumentManager::getSchedClassID(
// or (Opcode, LMUL, SEW) if SEW instrument is active, and depends on LMUL
// and SEW, or (Opcode, LMUL, 0) if does not depend on SEW.
uint8_t SEW = SI ? SI->getSEW() : 0;
- // Check if it depends on LMUL and SEW
- const RISCVVInversePseudosTable::PseudoInfo *RVV =
- RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
- // Check if it depends only on LMUL
- if (!RVV)
- RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
+
+ const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr;
+ if (Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V ||
+ Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V ||
+ Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V ||
+ Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V ||
+ Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V) {
+
----------------
wangpc-pp wrote:
Please remove this empty line.
https://github.com/llvm/llvm-project/pull/69409
More information about the llvm-commits
mailing list