[llvm] 65f946c - [RISCV] Fix some GlobalISel tests using -march instead of -mtriple.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2023-10-19T16:30:47-07:00
New Revision: 65f946cba4085d3d3054a0db3ed0e4006b6cf783

URL: https://github.com/llvm/llvm-project/commit/65f946cba4085d3d3054a0db3ed0e4006b6cf783
DIFF: https://github.com/llvm/llvm-project/commit/65f946cba4085d3d3054a0db3ed0e4006b6cf783.diff

LOG: [RISCV] Fix some GlobalISel tests using -march instead of -mtriple.

This caused llc to assume the wrong target triple and broke some internal
AS sanitizer bots.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir
index c45f10752f3755f..cf0baeb9527c955 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
 # RUN: -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            cmp_ult_i32

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir
index 1a4232db9754659..7b6506e738ee3c9 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/icmp-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
 # RUN: -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            cmp_ult_i64

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
index bc0395685b40e9e..a96f55fa66e1edd 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv32.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
 # RUN: -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            add_i32

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir
index d024a7c659878de..6346d913faf06b5 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/ptradd-rv64.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
 # RUN: -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            add_i64