[llvm] 460e843 - [RISCV] Add getSameRatioLMUL (#69570)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 19 10:52:46 PDT 2023
Author: Wang Pengcheng
Date: 2023-10-20T01:52:42+08:00
New Revision: 460e84398a19b8b662985e872a5e9762ca056a1b
URL: https://github.com/llvm/llvm-project/commit/460e84398a19b8b662985e872a5e9762ca056a1b
DIFF: https://github.com/llvm/llvm-project/commit/460e84398a19b8b662985e872a5e9762ca056a1b.diff
LOG: [RISCV] Add getSameRatioLMUL (#69570)
To calculate the LMUL with the same SEW/LMUL ratio when providing
EEW.
Added:
llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/unittests/Target/RISCV/CMakeLists.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index d71efc11e6a9fcf..7919189d198c8d1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -206,6 +206,15 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
return (SEW * 8) / LMul;
}
+RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
+ unsigned EEW) {
+ unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
+ unsigned EMULFixedPoint = (EEW * 8) / Ratio;
+ bool Fractional = EMULFixedPoint < 8;
+ unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
+ return RISCVVType::encodeLMUL(EMUL, Fractional);
+}
+
// Include the auto-generated portion of the compress emitter.
#define GEN_UNCOMPRESS_INSTR
#define GEN_COMPRESS_INSTR
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 20ff26a39dc3b30..e7181eadd497386 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -535,6 +535,8 @@ void printVType(unsigned VType, raw_ostream &OS);
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
+RISCVII::VLMUL getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
+ unsigned EEW);
} // namespace RISCVVType
namespace RISCVRVC {
diff --git a/llvm/unittests/Target/RISCV/CMakeLists.txt b/llvm/unittests/Target/RISCV/CMakeLists.txt
index 2c757b82e5dce85..9d0bf7244c02210 100644
--- a/llvm/unittests/Target/RISCV/CMakeLists.txt
+++ b/llvm/unittests/Target/RISCV/CMakeLists.txt
@@ -13,6 +13,7 @@ set(LLVM_LINK_COMPONENTS
add_llvm_target_unittest(RISCVTests
MCInstrAnalysisTest.cpp
+ RISCVBaseInfoTest.cpp
)
set_property(TARGET RISCVTests PROPERTY FOLDER "Tests/UnitTests/TargetTests")
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
new file mode 100644
index 000000000000000..0e4c90caaaefd7d
--- /dev/null
+++ b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
@@ -0,0 +1,34 @@
+//===- RISCVBaseInfoTest.cpp - RISCVBaseInfo unit tests ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/RISCVBaseInfo.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace {
+TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
+ // Smaller LMUL.
+ EXPECT_EQ(RISCVII::LMUL_1,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8));
+ EXPECT_EQ(RISCVII::LMUL_F2,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8));
+ // Smaller fractional LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F8,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_F4, 8));
+ // Bigger LMUL.
+ EXPECT_EQ(RISCVII::LMUL_2,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16));
+ EXPECT_EQ(RISCVII::LMUL_1,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
+ // Bigger fractional LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F2,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
+}
+} // namespace
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