[llvm] [AArch64][GlobalISel] Add support for post-indexed loads/stores. (PR #69532)

[Amara Emerson via llvm-commits]

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@@ -23615,6 +23617,23 @@ bool AArch64TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
   return CI->isTailCall();
 }
 
+bool AArch64TargetLowering::isIndexingLegal(MachineInstr &MI, Register Base,
+                                            Register Offset, bool IsPre,
+                                            MachineRegisterInfo &MRI) const {
+  // HACK
+  if (IsPre)
+    return false; // Until we implement.
+
+  auto CstOffset = getIConstantVRegVal(Offset, MRI);
+  if (!CstOffset || CstOffset->isZero())
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aemerson wrote:

Because then the G_PTR_ADD would be a NOP, and it wouldn't make sense for an pre/post-indexed load/store to add 0 to a base register.

https://github.com/llvm/llvm-project/pull/69532