[llvm] [RISCV] Add getSameRatioLMUL (PR #69570)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 19 09:38:56 PDT 2023
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/69570
>From 5bbd5e29649272ec2d20b01ecf6fd114f5cc14b2 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 19 Oct 2023 16:13:53 +0800
Subject: [PATCH 1/5] [RISCV] Add getSameRatioLMUL
To calculate the LMUL with the same SEW/LMUL ratio when providing
EEW.
---
.../RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 9 ++++++
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 ++
llvm/unittests/Target/RISCV/CMakeLists.txt | 1 +
.../Target/RISCV/RISCVBaseInfoTest.cpp | 30 +++++++++++++++++++
4 files changed, 42 insertions(+)
create mode 100644 llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index d71efc11e6a9fcf..4bfd44592d6d90e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -206,6 +206,15 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
return (SEW * 8) / LMul;
}
+RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
+ unsigned EEW, ) {
+ int Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
+ int EMULFixedPoint = (EEW * 8) / Ratio;
+ bool Fractional = EMULFixedPoint < 8;
+ unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
+ return RISCVVType::encodeLMUL(EMUL, Fractional);
+}
+
// Include the auto-generated portion of the compress emitter.
#define GEN_UNCOMPRESS_INSTR
#define GEN_COMPRESS_INSTR
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 20ff26a39dc3b30..e7181eadd497386 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -535,6 +535,8 @@ void printVType(unsigned VType, raw_ostream &OS);
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
+RISCVII::VLMUL getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
+ unsigned EEW);
} // namespace RISCVVType
namespace RISCVRVC {
diff --git a/llvm/unittests/Target/RISCV/CMakeLists.txt b/llvm/unittests/Target/RISCV/CMakeLists.txt
index 2c757b82e5dce85..9d0bf7244c02210 100644
--- a/llvm/unittests/Target/RISCV/CMakeLists.txt
+++ b/llvm/unittests/Target/RISCV/CMakeLists.txt
@@ -13,6 +13,7 @@ set(LLVM_LINK_COMPONENTS
add_llvm_target_unittest(RISCVTests
MCInstrAnalysisTest.cpp
+ RISCVBaseInfoTest.cpp
)
set_property(TARGET RISCVTests PROPERTY FOLDER "Tests/UnitTests/TargetTests")
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
new file mode 100644
index 000000000000000..3cc100c7b7c22c1
--- /dev/null
+++ b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
@@ -0,0 +1,30 @@
+//===- RISCVBaseInfoTest.cpp - RISCVBaseInfo unit tests ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/RISCVBaseInfo.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace {
+TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
+ // Smaller LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F2,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8));
+ // Smaller fractional LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F8,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_F4, 8));
+ // Bigger LMUL.
+ EXPECT_EQ(RISCVII::LMUL_2,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16));
+ // Bigger fractional LMUL.
+ EXPECT_EQ(RISCVII::LMUL_F2,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
+}
+} // namespace
\ No newline at end of file
>From 1eac44b5d56c8619a3bcdf9fb45cb32d0d86cd85 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 19 Oct 2023 16:19:28 +0800
Subject: [PATCH 2/5] fixup! [RISCV] Add getSameRatioLMUL
Remove comma and add more tests
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 2 +-
llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp | 6 +++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 4bfd44592d6d90e..fb1a83e88afd059 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -207,7 +207,7 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
}
RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
- unsigned EEW, ) {
+ unsigned EEW) {
int Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
int EMULFixedPoint = (EEW * 8) / Ratio;
bool Fractional = EMULFixedPoint < 8;
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
index 3cc100c7b7c22c1..b7eca94ad40959d 100644
--- a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
@@ -15,6 +15,8 @@ using namespace llvm;
namespace {
TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
// Smaller LMUL.
+ EXPECT_EQ(RISCVII::LMUL_1,
+ RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_2, 8));
EXPECT_EQ(RISCVII::LMUL_F2,
RISCVVType::getSameRatioLMUL(16, RISCVII::LMUL_1, 8));
// Smaller fractional LMUL.
@@ -23,8 +25,10 @@ TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
// Bigger LMUL.
EXPECT_EQ(RISCVII::LMUL_2,
RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_1, 16));
+ EXPECT_EQ(RISCVII::LMUL_1,
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
// Bigger fractional LMUL.
EXPECT_EQ(RISCVII::LMUL_F2,
- RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
}
} // namespace
\ No newline at end of file
>From 83f7848aec285f562abaf126864f61ea5f7af36a Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 19 Oct 2023 16:39:33 +0800
Subject: [PATCH 3/5] fixup! [RISCV] Add getSameRatioLMUL
Fix wrong tests
---
llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
index b7eca94ad40959d..06f7aad196c5896 100644
--- a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
@@ -29,6 +29,6 @@ TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
// Bigger fractional LMUL.
EXPECT_EQ(RISCVII::LMUL_F2,
- RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F2, 16));
+ RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
}
} // namespace
\ No newline at end of file
>From da7bde39e25809d6cd4ed1f74631b6b7651f27c4 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <137158460+wangpc-pp at users.noreply.github.com>
Date: Fri, 20 Oct 2023 00:34:51 +0800
Subject: [PATCH 4/5] Use `unsigned`
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index fb1a83e88afd059..7919189d198c8d1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -208,8 +208,8 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
unsigned EEW) {
- int Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
- int EMULFixedPoint = (EEW * 8) / Ratio;
+ unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
+ unsigned EMULFixedPoint = (EEW * 8) / Ratio;
bool Fractional = EMULFixedPoint < 8;
unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
return RISCVVType::encodeLMUL(EMUL, Fractional);
>From 86823b9ac06577ef3a2c36ab047ff2a83d6da655 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <137158460+wangpc-pp at users.noreply.github.com>
Date: Fri, 20 Oct 2023 00:38:45 +0800
Subject: [PATCH 5/5] Add newline to RISCVBaseInfoTest.cpp
---
llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
index 06f7aad196c5896..0e4c90caaaefd7d 100644
--- a/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
@@ -31,4 +31,4 @@ TEST(RISCVBaseInfo, CheckSameRatioLMUL) {
EXPECT_EQ(RISCVII::LMUL_F2,
RISCVVType::getSameRatioLMUL(8, RISCVII::LMUL_F4, 16));
}
-} // namespace
\ No newline at end of file
+} // namespace
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