[llvm] [AMDGPU] Constant fold FMAD_FTZ (PR #69443)

[Matt Arsenault via llvm-commits]

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@@ -5041,6 +5041,19 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
     return performAssertSZExtCombine(N, DCI);
   case ISD::INTRINSIC_WO_CHAIN:
     return performIntrinsicWOChainCombine(N, DCI);
+  case AMDGPUISD::FMAD_FTZ: {
+    SDValue N0 = N->getOperand(0);
+    SDValue N1 = N->getOperand(1);
+    SDValue N2 = N->getOperand(2);
+    EVT VT = N->getValueType(0);
+
+    // FMAD_FTZ is a FMAD, but flushing to zero is allowed (not required).
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arsenm wrote:

No, this is the node matching the instruction behavior. Just do the fold and flush it yourself 

https://github.com/llvm/llvm-project/pull/69443