[llvm] [RISCV][GlobalISel] Create generic instructions to handle legalization and selection of G_GLOBAL_VALUE for medlow code model (PR #69562)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 22:38:20 PDT 2023
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@@ -164,6 +164,25 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
preISelLower(MI, MIB, MRI);
const unsigned Opc = MI.getOpcode();
+ switch(Opc) {
+ case RISCV::G_RISCV_ADD_LO: {
+ Register DstReg = MI.getOperand(0).getReg();
+ const LLT XLenLLT = LLT::scalar(STI.getXLen());
+ RBI.constrainGenericRegister(DstReg, RISCV::GPRRegClass, MRI);
+ MI.setDesc(TII.get(RISCV::ADDI));
+ MRI.setType(DstReg, XLenLLT);
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topperc wrote:
Why do we need to call setType on a virtual register that's got a register class?
https://github.com/llvm/llvm-project/pull/69562
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