[llvm] f4231bf - [RISCV] Replace PostRAScheduler with PostMachineScheduler (#68696)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 22:30:45 PDT 2023
Author: Wang Pengcheng
Date: 2023-10-19T13:30:41+08:00
New Revision: f4231bf446ed8663886a86eb5b8b2db57baff854
URL: https://github.com/llvm/llvm-project/commit/f4231bf446ed8663886a86eb5b8b2db57baff854
DIFF: https://github.com/llvm/llvm-project/commit/f4231bf446ed8663886a86eb5b8b2db57baff854.diff
LOG: [RISCV] Replace PostRAScheduler with PostMachineScheduler (#68696)
Just like what other targets have done.
And this will make DAG mutations like MacroFusion take effect.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 1281528ea511a4d..651d24bae57263d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -248,6 +248,8 @@ class RISCVPassConfig : public TargetPassConfig {
public:
RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {
+ if (TM.getOptLevel() != CodeGenOptLevel::None)
+ substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
setEnableSinkAndFold(EnableSinkFold);
}
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 277951782ce5ccb..30b6e1e541394d0 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -159,7 +159,7 @@
; CHECK-NEXT: Insert KCFI indirect call checks
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
-; CHECK-NEXT: Post RA top-down list latency scheduler
+; CHECK-NEXT: PostRA Machine Instruction Scheduler
; CHECK-NEXT: Analyze Machine Code For Garbage Collection
; CHECK-NEXT: Machine Block Frequency Analysis
; CHECK-NEXT: MachinePostDominator Tree Construction
diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
index 18d1449d0e2e837..498e6cf23ba3495 100644
--- a/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
+++ b/llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
@@ -25,8 +25,8 @@ define void @foo(i32 signext %0, i32 signext %1) {
;
; FUSION-POSTRA-LABEL: foo:
; FUSION-POSTRA: # %bb.0:
-; FUSION-POSTRA-NEXT: lui a0, %hi(.L.str)
; FUSION-POSTRA-NEXT: fcvt.s.w fa0, a1
+; FUSION-POSTRA-NEXT: lui a0, %hi(.L.str)
; FUSION-POSTRA-NEXT: addi a0, a0, %lo(.L.str)
; FUSION-POSTRA-NEXT: tail bar at plt
%3 = sitofp i32 %1 to float
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