[llvm] [NewGVN][1/3] Load coercion between load and store (PR #68659)

[Konstantina Mitropoulou via llvm-commits]

================
@@ -653,6 +658,16 @@ class NewGVN {
   // Deletion info.
   SmallPtrSet<Instruction *, 8> InstructionsToErase;
 
+  // Map candidate load to their depending instructions.
+  mutable std::map<Value *, DenseSet<std::pair<Instruction *, BasicBlock *>>>
+      LoadCoercion;
+
----------------
kmitropoulou wrote:

In this patch, the load will only have one dependency. But, this is not the case for the other patches e.g.

```
Before load coercion
BB1:                                             BB2:                                             BB3:
 1 = MemoryDef(liveOnEntry)       2 = MemoryDef(liveOnEntry)     3 = MemoryDef(liveOnEntry)
 store i32 100, ptr %P                    store i32 500, ptr %P                  store i32 1000, ptr %P
 br label %BB4                               br label %BB4                             br label %BB4
                                         \                            |                                   /
                                                   BB4:
                                                      3 = MemoryPhi({BB1,1},{BB2,2},{BB3,3})
                                                      %V = load i32, ptr %P

After load coercion
BB1:                                             BB2:                                             BB3:
 1 = MemoryDef(liveOnEntry)       2 = MemoryDef(liveOnEntry)     3 = MemoryDef(liveOnEntry)
 store i32 100, ptr %P                    store i32 500, ptr %P                  store i32 1000, ptr %P
 br label %BB4                               br label %BB4                             br label %BB4
                                         \                            |                                   /
                                                   BB4:
                                                      %V = phi i32 [ 100, %BB1 ], [ 500, %BB2 ], [ 1000, %BB3 ]
 
```
Here, the load (%V) has three dependencies. Hence, the set will have the following pairs : (store i32 100, ptr %P, %BB1), (store i32 500, ptr %P, %BB2) and (store i32 1000, ptr %P, %BB3).


https://github.com/llvm/llvm-project/pull/68659