[llvm] [RISCV][GISel] Support G_PTRTOINT and G_INTTOPTR (PR #69542)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 17:45:11 PDT 2023
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/69542
Legalizer, register bank selection, and instruction selection.
Legalizer rules copied from AArch64.
>From b34374a4c711f92c43eb0968fe01422d89e5b0fc Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 18 Oct 2023 17:11:28 -0700
Subject: [PATCH] [RISCV][GISel] Support G_PTRTOINT and G_INTTOPTR
Legalizer, register bank selection, and instruction selection.
Legalizer rules copied from AArch64.
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 1 +
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 11 ++
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 2 +
.../instruction-select/int-ptr-cast-rv32.mir | 46 ++++++
.../instruction-select/int-ptr-cast-rv64.mir | 46 ++++++
.../legalizer/rv32/legalize-inttoptr.mir | 22 +++
.../legalizer/rv32/legalize-ptrtoint.mir | 125 +++++++++++++++
.../legalizer/rv64/legalize-inttoptr.mir | 22 +++
.../legalizer/rv64/legalize-ptrtoint.mir | 145 ++++++++++++++++++
.../GlobalISel/regbankselect/alu-rv32.mir | 48 +++++-
.../GlobalISel/regbankselect/alu-rv64.mir | 48 +++++-
11 files changed, 508 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 2d698736080d9fa..5717b62109be42a 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -180,6 +180,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
switch (Opc) {
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_PTRTOINT:
+ case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 475d8d5e3c6c791..32b00f32cc3e25b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -122,6 +122,17 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
getActionDefinitionsBuilder(G_PTR_ADD)
.legalFor({{p0, XLenLLT}});
+ getActionDefinitionsBuilder(G_PTRTOINT)
+ .legalFor({XLenLLT, p0})
+ .widenScalarToNextPow2(0, XLen)
+ .clampScalar(0, XLenLLT, XLenLLT);
+
+ getActionDefinitionsBuilder(G_INTTOPTR)
+ .unsupportedIf([&](const LegalityQuery &Query) {
+ return Query.Types[0].getSizeInBits() != Query.Types[1].getSizeInBits();
+ })
+ .legalFor({p0, XLenLLT});
+
getActionDefinitionsBuilder(G_BRCOND)
.legalFor({XLenLLT})
.minScalar(0, XLenLLT);
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index c8073199ade1bd3..4ede55fc8c54f68 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -126,6 +126,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_UREM:
case TargetOpcode::G_UMULH:
case TargetOpcode::G_PTR_ADD:
+ case TargetOpcode::G_PTRTOINT:
+ case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_SEXT:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
new file mode 100644
index 000000000000000..9a56020006b09c3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrtoint_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: ptrtoint_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s32) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoptr_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: inttoptr_s32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s32) = COPY $x10
+ %1:gprb(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
new file mode 100644
index 000000000000000..4f8259e69553602
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: ptrtoint_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: ptrtoint_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(p0) = COPY $x10
+ %1:gprb(s64) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoptr_s64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: inttoptr_s64
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: $x10 = COPY [[COPY]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:gprb(s64) = COPY $x10
+ %1:gprb(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir
new file mode 100644
index 000000000000000..24de9512e0b7fc1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-inttoptr.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir
new file mode 100644
index 000000000000000..9fba2dd9629de23
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ptrtoint.mir
@@ -0,0 +1,125 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s16) = G_PTRTOINT %0(p0)
+ %2:_(s32) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s8
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s8) = G_PTRTOINT %0(p0)
+ %2:_(s32) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s1
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s1) = G_PTRTOINT %0(p0)
+ %2:_(s32) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_PTRTOINT %0(p0)
+ %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
+ $x10 = COPY %2(s32)
+ $x11 = COPY %3(s32)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: p0_s44
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s44
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s44) = G_PTRTOINT %0(p0)
+ %4:_(s32) = G_TRUNC %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir
new file mode 100644
index 000000000000000..801e6fd8b7005b3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-inttoptr.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %1(p0)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir
new file mode 100644
index 000000000000000..7299c5963146bc3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ptrtoint.mir
@@ -0,0 +1,145 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: p0_s64
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s64
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s32
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s32
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s32)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s16
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s16
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s16) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s16)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s8
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s8
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s8) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s8)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s1
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s1
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s1) = G_PTRTOINT %0(p0)
+ %2:_(s64) = G_ANYEXT %1(s1)
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: p0_s128
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s128
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: $x11 = COPY [[C]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(p0) = COPY $x10
+ %1:_(s128) = G_PTRTOINT %0(p0)
+ %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(s128)
+ $x10 = COPY %2(s64)
+ $x11 = COPY %3(s64)
+ PseudoRET implicit $x10, implicit $x11
+
+...
+---
+name: p0_s88
+body: |
+ bb.0:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: p0_s88
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s88) = G_PTRTOINT %0(p0)
+ %4:_(s64) = G_TRUNC %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
index 6f8d76953de4fb7..1677c734eb9171e 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -408,14 +408,54 @@ body: |
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s32)
- ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
- ; RV32I-NEXT: $x10 = COPY [[COPY2]](p0)
+ ; RV32I-NEXT: $x10 = COPY [[PTR_ADD]](p0)
; RV32I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(p0) = G_PTR_ADD %0, %1(s32)
- %3:_(p0) = COPY %2(p0)
- $x10 = COPY %3(p0)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: ptrtoint
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV32I-LABEL: name: ptrtoint
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV32I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0)
+ ; RV32I-NEXT: $x10 = COPY [[PTRTOINT]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s32) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoprt
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV32I-LABEL: name: inttoprt
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+ ; RV32I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32)
+ ; RV32I-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s32)
+ $x10 = COPY %1(p0)
PseudoRET implicit $x10
...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
index 26120f770413623..701f3d49ed85b65 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -429,14 +429,54 @@ body: |
; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64)
- ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
- ; RV64I-NEXT: $x10 = COPY [[COPY2]](p0)
+ ; RV64I-NEXT: $x10 = COPY [[PTR_ADD]](p0)
; RV64I-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s64) = COPY $x11
%2:_(p0) = G_PTR_ADD %0, %1(s64)
- %3:_(p0) = COPY %2(p0)
- $x10 = COPY %3(p0)
+ $x10 = COPY %2(p0)
+ PseudoRET implicit $x10
+
+...
+---
+name: ptrtoint
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV64I-LABEL: name: ptrtoint
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+ ; RV64I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s64) = G_PTRTOINT [[COPY]](p0)
+ ; RV64I-NEXT: $x10 = COPY [[PTRTOINT]](s64)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(p0) = COPY $x10
+ %1:_(s64) = G_PTRTOINT %0(p0)
+ $x10 = COPY %1(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: inttoprt
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $x10
+
+ ; RV64I-LABEL: name: inttoprt
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+ ; RV64I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s64)
+ ; RV64I-NEXT: $x10 = COPY [[INTTOPTR]](p0)
+ ; RV64I-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(p0) = G_INTTOPTR %0(s64)
+ $x10 = COPY %1(p0)
PseudoRET implicit $x10
...
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