[llvm] [AMDGPU] Allow lit() on operands which do not accept modifiers (PR #69527)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 18 14:27:00 PDT 2023
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/69527
None
>From 2aea55b55c9892a72cd35a13d37c6efe9c17e0e6 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Wed, 18 Oct 2023 14:24:28 -0700
Subject: [PATCH] [AMDGPU] Allow lit() on operands which do not accept
modifiers
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 38 +++++++++++++++----
llvm/test/MC/AMDGPU/literals.s | 10 +++++
2 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index faeaa94f9733576..6473e4ce9566f35 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1577,9 +1577,11 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;
bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;
bool parseSP3NegModifier();
- ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);
+ ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false,
+ bool HasLit = false);
ParseStatus parseReg(OperandVector &Operands);
- ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);
+ ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false,
+ bool HasLit = false);
ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,
bool AllowImm = true);
ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,
@@ -2904,13 +2906,26 @@ AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
}
ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
- bool HasSP3AbsModifier) {
+ bool HasSP3AbsModifier, bool HasLit) {
// TODO: add syntactic sugar for 1/(2*PI)
if (isRegister())
return ParseStatus::NoMatch;
assert(!isModifier());
+ if (!HasLit) {
+ HasLit = trySkipId("lit");
+ if (HasLit) {
+ if (!skipToken(AsmToken::LParen, "expected left paren after lit"))
+ return ParseStatus::Failure;
+ ParseStatus S = parseImm(Operands, HasSP3AbsModifier, HasLit);
+ if (S.isSuccess() &&
+ !skipToken(AsmToken::RParen, "expected closing parentheses"))
+ return ParseStatus::Failure;
+ return S;
+ }
+ }
+
const auto& Tok = getToken();
const auto& NextTok = peekToken();
bool IsReal = Tok.is(AsmToken::Real);
@@ -2923,6 +2938,9 @@ ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
Negate = true;
}
+ AMDGPUOperand::Modifiers Mods;
+ Mods.Lit = HasLit;
+
if (IsReal) {
// Floating-point expressions are not supported.
// Can only allow floating-point literals with an
@@ -2941,6 +2959,8 @@ ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
Operands.push_back(
AMDGPUOperand::CreateImm(this, RealVal.bitcastToAPInt().getZExtValue(), S,
AMDGPUOperand::ImmTyNone, true));
+ AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
+ Op.setModifiers(Mods);
return ParseStatus::Success;
@@ -2967,7 +2987,11 @@ ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
if (Expr->evaluateAsAbsolute(IntVal)) {
Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
+ AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
+ Op.setModifiers(Mods);
} else {
+ if (HasLit)
+ return ParseStatus::NoMatch;
Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
}
@@ -2990,20 +3014,20 @@ ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
}
ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
- bool HasSP3AbsMod) {
+ bool HasSP3AbsMod, bool HasLit) {
ParseStatus Res = parseReg(Operands);
if (!Res.isNoMatch())
return Res;
if (isModifier())
return ParseStatus::NoMatch;
- return parseImm(Operands, HasSP3AbsMod);
+ return parseImm(Operands, HasSP3AbsMod, HasLit);
}
bool
AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
if (Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::LParen)) {
const auto &str = Token.getString();
- return str == "abs" || str == "neg" || str == "sext" || str == "lit";
+ return str == "abs" || str == "neg" || str == "sext";
}
return false;
}
@@ -3123,7 +3147,7 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
ParseStatus Res;
if (AllowImm) {
- Res = parseRegOrImm(Operands, SP3Abs);
+ Res = parseRegOrImm(Operands, SP3Abs, Lit);
} else {
Res = parseReg(Operands);
}
diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s
index 910e3d82b2fc849..00575619c49f658 100644
--- a/llvm/test/MC/AMDGPU/literals.s
+++ b/llvm/test/MC/AMDGPU/literals.s
@@ -925,3 +925,13 @@ v_sqrt_f32 v2, lit(123.0
// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: expected immediate with lit modifier
// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: expected immediate with lit modifier
v_sqrt_f32 v2, lit(v1)
+
+// Make sure lit() is accepted on operands without modifiers.
+
+// SICI: v_madak_f32 v4, 0x7e8, v8, 0x7e8 ; encoding: [0xff,0x10,0x08,0x42,0xe8,0x07,0x00,0x00]
+// GFX89: v_madak_f32 v4, 0x7e8, v8, 0x7e8 ; encoding: [0xff,0x10,0x08,0x30,0xe8,0x07,0x00,0x00]
+v_madak_f32 v4, lit(0x7e8), v8, lit(0x7e8)
+
+// NOSICI: :[[@LINE+2]]:{{[0-9]+}}: error: not a valid operand.
+// NOGFX89: :[[@LINE+1]]:{{[0-9]+}}: error: not a valid operand.
+v_madak_f32 v4, lit(lit(0x7e8)), v8, lit(0x7e8)
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