[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

================
@@ -1015,17 +1015,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       break;
     // If the mask has 32 trailing ones, use SRLIW.
----------------
topperc wrote:

Update comment

https://github.com/llvm/llvm-project/pull/69416