[llvm] Add RV64 constraint to SRLIW (PR #69416)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 17 23:00:20 PDT 2023


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@@ -1015,17 +1015,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       break;
     // If the mask has 32 trailing ones, use SRLIW.
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topperc wrote:

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https://github.com/llvm/llvm-project/pull/69416


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