[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

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@@ -1015,10 +1015,17 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       break;
     // If the mask has 32 trailing ones, use SRLIW.
     if (TrailingOnes == 32) {
-      SDNode *SRLIW =
-          CurDAG->getMachineNode(RISCV::SRLIW, DL, VT, N0->getOperand(0),
-                                 CurDAG->getTargetConstant(ShAmt, DL, VT));
-      ReplaceNode(Node, SRLIW);
+      if (Subtarget->is64Bit()) {
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topperc wrote:

Can we just select the opcode using `Subtarget->is64Bit()` instead of duplicating similar code?

https://github.com/llvm/llvm-project/pull/69416