[llvm] Add RV64 constraint to SRLIW (PR #69416)

[Craig Topper via llvm-commits]

================
@@ -1232,7 +1233,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
 
       // Turn (and (shr x, c2), c1) -> (slli (srli x, c2+c3), c3) if c1 is a
       // shifted mask with c2 leading zeros and c3 trailing zeros.
-      if (!LeftShift && isShiftedMask_64(C1)) {
+      if (!LeftShift && isShiftedMask_64(C1) && Subtarget->is64Bit()) {
----------------
topperc wrote:

Doesn't this block the case where `SrliOpc` stays as `RISCV::SRLI` on RV32?

https://github.com/llvm/llvm-project/pull/69416