[llvm] b427388 - [PowerPC] Auto gen test checks for #69299. NFC.
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 17 19:22:49 PDT 2023
Author: Kai Luo
Date: 2023-10-18T02:21:22Z
New Revision: b42738805acffafee158b56320d725e51908761f
URL: https://github.com/llvm/llvm-project/commit/b42738805acffafee158b56320d725e51908761f
DIFF: https://github.com/llvm/llvm-project/commit/b42738805acffafee158b56320d725e51908761f.diff
LOG: [PowerPC] Auto gen test checks for #69299. NFC.
Added:
Modified:
llvm/test/CodeGen/PowerPC/crbit-asm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/crbit-asm.ll b/llvm/test/CodeGen/PowerPC/crbit-asm.ll
index ffd8cb10f830d5e..617d6ec27b63f5e 100644
--- a/llvm/test/CodeGen/PowerPC/crbit-asm.ll
+++ b/llvm/test/CodeGen/PowerPC/crbit-asm.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
@@ -7,29 +8,71 @@ target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
+; CHECK-LABEL: testi1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi. 3, 3, 1
+; CHECK-NEXT: crmove 20, 1
+; CHECK-NEXT: andi. 3, 4, 1
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: crand 20, 20, 1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: isel 3, 4, 3, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi1:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
+; CHECK-NO-ISEL-NEXT: crmove 20, 1
+; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
+; CHECK-NO-ISEL-NEXT: li 3, 0
+; CHECK-NO-ISEL-NEXT: li 4, 1
+; CHECK-NO-ISEL-NEXT: #APP
+; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
+; CHECK-NO-ISEL-NEXT: #NO_APP
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
%1 = and i8 %0, 1
%tobool3 = icmp ne i8 %1, 0
ret i1 %tobool3
-; CHECK-LABEL: @testi1
-; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
-; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
-; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
-; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], 1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
-; CHECK-NO-ISEL-LABEL: @testi1
-; CHECK-NO-ISEL: bc 12, 20,
-; CHECK-NO-ISEL: blr
-; CHECK-NO-ISEL: addi 3, 4, 0
-; CHECK-NO-ISEL-NEXT: blr
-; CHECK: blr
}
define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
+; CHECK-LABEL: testi32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi. 3, 3, 1
+; CHECK-NEXT: crmove 20, 1
+; CHECK-NEXT: andi. 3, 4, 1
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, -1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: crand 20, 20, 1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: isel 3, 4, 3, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi32:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
+; CHECK-NO-ISEL-NEXT: crmove 20, 1
+; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
+; CHECK-NO-ISEL-NEXT: li 3, 0
+; CHECK-NO-ISEL-NEXT: li 4, -1
+; CHECK-NO-ISEL-NEXT: #APP
+; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
+; CHECK-NO-ISEL-NEXT: #NO_APP
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
ret i32 %0
@@ -37,31 +80,41 @@ entry:
; The ABI sign_extend should combine with the any_extend from the asm result,
; and the result will be 0 or -1. This highlights the fact that only the first
; bit is meaningful.
-; CHECK-LABEL: @testi32
-; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
-; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
-; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
-; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], -1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
-; CHECK: blr
}
define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
+; CHECK-LABEL: testi8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi. 3, 3, 1
+; CHECK-NEXT: crmove 20, 1
+; CHECK-NEXT: andi. 3, 4, 1
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: li 4, 1
+; CHECK-NEXT: #APP
+; CHECK-NEXT: crand 20, 20, 1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: isel 3, 4, 3, 20
+; CHECK-NEXT: blr
+;
+; CHECK-NO-ISEL-LABEL: testi8:
+; CHECK-NO-ISEL: # %bb.0: # %entry
+; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
+; CHECK-NO-ISEL-NEXT: crmove 20, 1
+; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
+; CHECK-NO-ISEL-NEXT: li 3, 0
+; CHECK-NO-ISEL-NEXT: li 4, 1
+; CHECK-NO-ISEL-NEXT: #APP
+; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
+; CHECK-NO-ISEL-NEXT: #NO_APP
+; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1
+; CHECK-NO-ISEL-NEXT: blr
+; CHECK-NO-ISEL-NEXT: .LBB2_1: # %entry
+; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
+; CHECK-NO-ISEL-NEXT: blr
entry:
%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
ret i8 %0
-; CHECK-LABEL: @testi8
-; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
-; CHECK-DAG: li [[REG1:[0-9]+]], 0
-; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
-; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
-; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
-; CHECK-DAG: li [[REG4:[0-9]+]], 1
-; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
-; CHECK: blr
}
attributes #0 = { nounwind "target-features"="+crbits" }
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